Basic 4 Bit Parallel Adder Computer Science Essay

The main aim of the project is to develop a basic 4-bit parallel adder using carry look- ahead logic. In this project research we obtain knowledge about functional description of adder in parallel process of addition, subtraction and developing at its fastest speed of addition. Basic reason is adders are basic components in any operation so if we develop the adders at high efficiently at high speed performances we change the technology nature rapidly. Carry Look Ahead Adder is developed such that to increase the speed by reducing the delay caused by waiting for carry in a basic ripple carry adder at each stage as carryout will be feed back as the next stage carry input.

Model architecture of a 4-bit carry look-ahead adder, which is works developed based on carry look ahead logic. CLA logic is nothing but producing final carryout independent of intermediate carry feeding i.e., we find carryout by only depending on initial carry input and input bits value.

Thus a carry look-ahead adder developed in 3 generator stages. They are propagate generator, carry generator (CLA logic) and sum generator. Such that there is no more such a delay developed cause by carry waiting at each stage. We can find carryout at each stage independent to sum output at present stage and generated carry at previous stage so in CLA adder operated as a perfect parallel process with respect to the initial values.

The developed logic will be implemented as a schematic using mentor graphics software. The function of CLA logic tested from obtained waveforms.

The performance and delay will be calculated and verified with truth table of different combination addition process even a carry feedback for the next stage 4-bit addition looping mechanism as well developed for a continuous process.

Layout of CLA adder will be designed as a blue print for final IC design blue-print.

1. Introduction

The generation of technology developing in a rapid speed. That to approximately every six months a new generation such that every thing depends on the speed of processing. So every thing depends on data processing i.e., functional speed. In the end they need to speed-up operational speed. basically to do any arithmetic or logical operation Adder is a basic element. All the operations in control systems and digital system followed by addition. As we deal with binary 0 & 1 ‘s all operations must be done in addition. Therefore in addition we need adders. In any operation, what ever may be the technology adders are the basic elements. So how fast and efficient the adder works will effect every thing in the system. Such that adders are developed for different applications in different way.

Adders are half adder, full adder and serial and parallel adders

All these adders used based on the application depending on the time delays, power consumption and architecture designs. But all adders based on the CMOS technology such their parameters are all most same.

Carry Look-Ahead adder is a parallel adder, in which carry will be calculated independent to the previous stage carry that to directly from given inputs. Thus addition by using CLA logic will made faster than ripple carry adder in which delay caused by carry feed to the next stage. Thus delay reduced by parallel processing at each stage.

CLA adder consists of three generator blocks. They are propagation generator, carry generator and sum generator where each stage followed by others respectively. Thus we get the sums and final carry out faster than basic adders.

2. BACKGROUND

2.1 Addition:

Addition is a process of adding bits. Binary addition means adding binary bits 0’s and 1’s and sum and carry generated in binary farm in any signal processing. Now lets consider the 4-bit addition example,

As shown above A and B bits added giving Sum out by rippling the carry at each stage and C4 as final carry obtained.

2.2 Subtraction:

Subtraction is a process of adding a positive bit to the negative bit. Negative of a bit means 2’s compliment of it. This is nothing but adding 1 bit to LSB of its 1’s compliment. 1’s compliment is nothing but reversing the logic of the bits. Now lets consider the 4-bit subtraction example,

The above subtraction technique dedicated to the subtracting a smaller binary from a larger binary. If it changes it just followed by few more steps as change sign bit (MSB) to zero, then change it to its 2’s compliment as before process.

2.3 Half Adder:

Half adder is the adder which is used to add two bits and its outputs as sum and carry of bits. Half adder build by EXOR gate for sum of bits and AND gate used for carry of the bits. We construct using Karnaugh-mapping.

If A, B are adder inputs then Sum, S and Carry, C0 are,

Sum = A.B’ + A’.B =A xor B

Carry = A . B

2.4 XOR GATE:

XOR is also called Exclusive OR gate or EOR gate. This is a digital logic gate, which is used to express the function of Exclusive Disjunction. Its behavior is similar to or gate with exclusive condition. Usually it is a 2-1 input output IC respectively.

An output HIGH (1) will be resulted if one, and only one of its 2 inputs is HIGH (1). Result of output LOW (0) both the inputs should be same either low or high. We can say EX-OR gate as “One or another, but not both”.

XOR gate is used to develop a binary addition. It gives the sum for given input bits. As shown above xor of 2 bits A and B gives its sum.

A xor B = A.B’ + A’.B

Its logic symbol and NAND gate representation is shown below.

2.5 Full adder (1-bit serial adder):

Full adder is used to add three binary bits together and their sum and carry given as its outputs. Full adder is constructed by two cascaded half adders followed by or gate. we construct using k-mapping i.e., EXOR product of bits gives sum output of the bits and carry from two and gate and followed by a or gate.

Below figure shows the Full Adder constructed by 2 Half Adders cascaded by an OR gate. It is a binary bit adder, which is used to add 3-binary bits at a time.

If A, B and CI are adder inputs then Sum and Carry are,

S = (A+B+CI) + (A.B.CI) = CI xor A xor B

CO = B . CI + A . CI + A . B = CI . (A + B) + A . B

= CI . (A xor B) + A . B

From above truth table we can draw K-Mapping for Sum and Carry terms from the followed inputs A, B and CI.

2.6 Serial adder:

Serial adder is a single full adder that is used to add two bits of data at a time by carry feed back to next stage of the inputs. In this carry will be stored for a bit of time using D-Flip flop and feed back so that the single full adder circuit is operated to add stream of 2 inputs data will be added one by one. Such that finally one carry out generated at the end and sum bits generated at each stage of input bits. This is a practical full adder that used to add a stream of two bits addition. It takes LSB bits first in addition. This is a very simple way of addition such that serial and less complex but much delayed operation.

As shown above serial adder is like a single bit full adder, where the Cout feeded to the next stage of Cin. Such that serial adder is a simple and a bit delays expected in the feed back looping. But at low speed this is a perfect adder as it constructed cheaper and simple.

If Ai, Bi and Ci are the adder inputs then Si and Ci+1 are,

Si = Ci xor Ai xor Bi

Ci+1 = Bi . Ci + Ai . Ci + Ai . Bi = Ci . (Ai xor Bi) + Ai . Bi

The output is sum at each stage sums and a final catty output after all bits addition finished, even we get each stage carry output for reference.

2.7 D- Flip Flop:

D Flip-Flop is the most popular Flip-Flop. As its output takes the value of data ( D ) input when the positive edge of clock pulse. D Flip-flop has 1-data input and 1-clock pulse input and outputs are Q for D input with one clock period delay and QN is inverted form of D input. D Flip-flop can be interpreted as a primitive memory cell.

D Flip-flops are basically used as Shift registers. As a D Flip-flop can produce a output signal with a time period delay of given clock pulse for an input signal i.e., one bit shifted right to the input given signal. The principle of D flip-flop is it captures the signal at the moment the clock goes high, and subsequent changes of the data lines do not influence Q until the rise of next clock edge. thus its works as a edge triggering mode at clock signal rising.

D Flip-flop is constructed using NAND gates as shown above, where D and CLOCK are the inputs and Q and QN are the out puts. The Truth Table and logic symbol is shown below.

2.8 RIPPLE CARRY ADDER (Basic Parallel adder):

Parallel adders are digital circuits that compute the addition of variable binary strings of equivalent or different size in parallel. Parallel adder is nothing but a combination of Full adders as cascaded each other by connecting carry out of an adder to another carry in of next stage adder. In this we do more than one bit addition at a time so it going to be quicker than others. The full adder feed by carry at each stage of bit, so in simple ripple carry or carry propagate adder delay for the carry at each stage will be high. Therefore the waiting delay for each stage of carry makes adder very delayed. Such that ripple carry adder takes much delay but it is simplest and efficient design to use in low level systems. Where delay is multiple of n Full adders.

The schematic diagram of a parallel adder is shown below.

As shown in above a Ripple Carry Adder is constructed in cascaded stages of full adders, such that as we allow a parallel processing of addition but only delay occurred by waiting of next stage next stage carry in. Outputs are sum at each stage and a final carry out will obtained as shown.

If Ai, Bi, Ci are the adder stage inputs then, sum Si and carry out for next stage Ci+1 are, ( As like a serial adder out puts)

Si = Ci xor Ai xor Bi

Ci+1 = Bi. Ci + Ai . Ci + Ai . Bi = Ci . ( Ai + Bi ) + Ai . Bi

2.9 Carry Look-ahead Adder:

From Ripple Carry adder, Such that to avoid the delay at each stage, other way is to find carry at each stage in advance that independent to intermediate carry from the previous stage just depending on the initial input values. Where, no more delay at each stage occurred by carry feed back from previous stages and all the operations done at same time delay so there will be no much fluctuations in out comes.

As shown above it is model architecture of a 4-bit carry look ahead adder, developed in 3 generator stages. First stage is propagate generator, middle stage is carry generator and it followed by final stage sum generator .We can find carryout at each stage independent to sum output at present stage and generated carry at previous stage so in CLA adder operated as a perfect parallel process with respect to the initial values. The result is a reduced carry propagation time.

3. 4-bit CLA adder developed in Conventional logic

To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G are first half adder stage in a full-adder, is given as:

If A and B are the inputs and C0 is carry input for a full adder then,

Carry out = A.C0 + B.C0 + A.B

Sum = A xor B xor C0

But at each stage, P and G generator is a half adder.

Pi = Ai xor Bi Carry propagate

Gi = Ai . Bi Carry generate

Notices that both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay.

The new expressions for the output sum and the carryout are given by:

Si = Pi xor Ci-1

Ci+1= Gi + PiCi

These equations show that a carry signal will be generated in two cases:

1) If both bits Ai and Bi are 1

2) If either Ai or Bi is 1 and the carry-in Ci is 1.

Let’s apply these equations for a 4-bit adder:

C1 = G0 + P0C0

C2 = G1 + P1C1 = G1 + P1(G0 + P0C0)

= G1 + P1G0 + P1P0C0

C3 = G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)

= G2 + P2G1 + P2P1G0 + P2P1P0C0

C4 = G3 + P3C3 = G3 + P3 (G2 + P2G1 + P2P1G0 + P2P1P0C0)

= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 …..C3.

The general expression is:

Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 ….P1P0C0.

As shown below the architecture of a Carry Look-Ahead adder will be constructed from the following derivations above such that in three stages, As the first stage as PG generator then followed by others. Where just after one gate delay we go to carry generator and sum generator simultaneously when it get the next stage carry. Such that it generates the sum and carry out parallel operation.

Above showed architecture of a fast CLA Adder but, we have a problem while constructing in Mentor Graphics software core library as max no. of input pin for NAND and NOR is 4 to 1. So we changed C4 as shown below Constructed CLA Adder in Mentor Graphics software with out much changes in speed and efficiency at best computation.

Such that C4 can be changed as,

Here the CLA adder is restricted to 4-bit parallel adder because as we go to the next stage such that 8-bit the CLA becomes not only complex it will be massive architecture. So we may get a bit faster but its almost negligible and even useless when compared to ripple carry adder. The efficiency will be very low and much delay as we use massive gates.

Such that 4-bit CLA is a best design and it will be universal CLA. For a 8-bit or 16 bit and even more bit CLA adder we use multiple 4-bit CLAs cascaded each other by feeding carry from previous stage and even it is always better than a ripple carry adder.

4. NAND gate architecture of CLA adder

From the above obtained mechanism looks very good concept of developing CLA Adder but we have a big difficulty in achieving the speed in which the carry propagate and generate are not basic universal gates. So there is much gate delays are expected at each stage, and even more power dissipation and less efficiency. The main draw back is propagate generator is a Half Adder, so final carry will be much delayed as simple ripple carry in some cases not effective.

Now we need to approach for a better CLA logic which based almost on basic universal gates. Research as follows,

Such that we need to develop the CLA logic using the basic universal gates at the initial propagate generator stage. Then only we can reduce the delay at a great extent. Even we get better efficiency.

In Mentor Graphics v.2005 software lab maximum pins available is 4-1 NAND in Core Library, so we have to change the C4 such that we can construct in mentor Graphics.

From the above research of better CLA logic we developed a best CLA Adder as we using the most of universal adders in operation.

The main concept involved in this research is using the best gate out of universal gates NAND and NOR gates in CMOS Transistor architecture.

So we developed by using NAND gate architecture of CLA adder.

As we know,

Diffusion constant of holes is always less than electrons.

In PMOS Transistor holes are majority carriers and in NMOS transistor electrons are majority carriers.

Holes, which represents an empty space in atom. An electron occupies this empty space leaving a hole, the same occurs for this empty hole. This results in an effective movement across semiconductor.

As electron mobility faster than hole mobility, NMOS Transistor is faster than PMOS Transistor as small electrons offer less resistance.

4.1 CMOS logic

Such that we developed CMOS Technology by combination of Pull-up network of PMOS Transistors and Pull-down network of NMOS Transistors. All the CMOS gates are constructed using as shown below.

CMOS Constructed by, PMOS transistors in Pull-up network stage and NMOS transistors in Pull-down network stage.

OUTPUT going 1->0

 The Pull-down NMOS transistors discharges the output capacitance.

OUTPUT going 0->1

The output capacitance is charged through Pull-up PMOS transistors.

CMOS logic is better logic than PMOS and NMOS implementations individually. Because PMOS transistors are great at transmitting a logic 0 to1 voltage without signal loss, NMOS transistors are great at transmitting a logic 1 to 0 voltage.

4.2 NAND GATE:

Constructed by, As shown above PMOS transistors in parallel and NMOS transistors in series.

OUTPUT going 1->0

 The series NMOS transistors discharges the output capacitance.

OUTPUT going 0->1

The output capacitance is charged through parallel PMOS transistors.

4.3 NOR GATE:

Constructed by, As shown NMOS transistors in parallel and PMOS transistors in series.

OUTPUT going 1->0

 The parallel NMOS transistors discharges the output capacitance.

OUTPUT going 0->1

  The output capacitance is charged through series PMOS transistors.

4.4 Why NAND gate is BEST,

As PMOS in parallel and NMOS in series the resultant transition delay at NAND gate is lesser than delay of NOR gate architecture.

To make PMOS as fast as NMOS we need enlarge channel and P-regions, but that leads to large silicon layout, and more cost and power wastage. So At same speed NOR is always larger than NAND. So it makes NAND more efficient than NOR. W/L ratio of NAND gate is smaller than NOR gate.

If inputs for gates are more then, NAND will be very faster than NOR.

So we use sop implementation rather than pos.

Thus we get a faster CLA logic developed NAND gate architecture of CLA Adder is shown below. This is faster in operation and efficient than all ICs discussed above.

Where inputs A0, A1, A2 and A3 are A bits and B0, B1, B2 and B3 are B bits. The outputs of CLAA are as S0, S1, S2 and S3 are Sum bits and C4 is the final Carry out.

This CLA Adder IC thermal and electrical properties are as same as CMOS ICs, as it developed using CMOS Technology.

For the 4-bit serial CLA Adder can be constructed based on 1-bit serial adder concept, by feeding C4 to the next stage bits addition using Flip-Flop at proper clock speed (i.e., half to input data rate).

For the 8-bit CLA Adder can be constructed based on parallel adder concept, by cascading adders on another and feeding C4 to next stage carry input.

The architecture is a fast CLA Adder but, we have a problem while constructing in Mentor Graphics software core library as max no. of input pin for NAND and NOR is 4 to 1. So we changed C4 as shown below Constructed CLA Adder in Mentor Graphics software with out much changes in speed and efficiency at best computation.

Where inputs A0, A1, A2 and A3 are A bits and B0, B1, B2 and B3 are B bits. The outputs of CLAA are as S0, S1, S2 and S3 are Sum bits and C4 is the final Carry out.

In the below shown circuit diagram, it works as both single bits of 4-bit CLA adder and a serial 4-bit CLA adder by just changing the clock.

For single bits CLA logic we need to keep the D flip-flop disable, such that we have to keep clock input kept always low logic or make it as no clock. Thus it adds given input bits without any feeding if C4 to C0. So we can even give C0 to any logic such that we can use it in any stage of adder application.

When considering the D flip-flop input, IC pins will be extra adder as flip-flop inputs D and clock and its out put pins Q and QN, where Q is primary usage port.

4.5 4-bit CLA adder developed in NAND gate

In practical implementation of C|LA adder will be implemented in series or parallel combination. Such that in practical application above design is a better way of developing a universal 4-bit parallel CLA adder.

4.5 Serial adder of 4-bit CLA logic

Serial adder of 4-bit CLA adder is implemented as a single bit adder technique. By feeding Carry out of present stage to next stage carry in of input bits.

As shown below serial 4-bit parallel adder is implemented.

In the above shown serial CLA adder, i represent stages as i+1 is the next stage. A and B are the 4-bit inputs A0 to A3 and B0 to B3. Similarly Sum output S is the 4-bit output as S0 to S3. Ci is the input carry at that stage and at initial condition it is C0 as zero. Ci+1 is the carry out for the CLA Adder at i th stage usually it is a C4 output carry of CLA Adder.

Thus above serial adder of CLA is used to add 4-bit parallel data inputs and output sum of bits and final carry of 4-bits at each stage.

In shown before CLA implementation for a proper clock input of D flip-flop it works as a serial 4-bit CLA adder. But make sure that given clock should be a clock synchronized to the input bits A and B. C0 will be given as logic 0 automatically because of next clock rise output delay. Such that it works as a dynamic serial adder.

4.6 Ripple carry adder by CLA Adder logic

Ripple carry 4-bit CLA adder is be constructed by using same technique as basic ripple carry adder. Such that at each stage of adder carry out is rippled to the next stage of carry input. As shown below we can construct 16-bit ripple carry CLA Adder is parallel adder logic. Such that CLA Adder is developed as a IC that can be used in serial as well as in parallel processing of addition. It will be constructed as shown below.

Above 16-bit ripple carry 4-bit CLA Adder inputs are 16-bit individual A and B bits and their added sum is 16-bit output and final carry C16 is obtained through rippling C4, C8, C12 Carryout puts at intermediate stages.

Thus as shown above design works at its best speed as a 4-bit CLA adder is a fast and efficient adder so the delay at each stage is lesser than basic adder. So developing any logic in adder types we can use CLA logic as basic component. Such that in developing logic of carry skip adder, carry select adder and carry save adder, where they use a 4-bit wise block developed at each stage using their respective logics i.e., 4-bit CLA adder is a basic component. So CLA Compinent logic is a basic and best logic in developing any stage of adders.

5. 4-bit CLA adder/subtractor* logic developed using NAND gate (lower from higher):

Addition is adding positive two bits. Subtraction is nothing but an addition where we add one positive bit to another negative bit. That means the second bit will be the positive number with negative polarity. We can convert positive binary to negative binary by its 2’s compliment.

2’s compliment is nothing but adding 1 bit to the LSB side of 1’s compliment.

1’s compliment is in any binary code if we swap bits by 1 bit with 0 bit and 0 bit with 1 bit. That is flip the binary code image.

1’s compliment can be generated using an EXOR logic. when we give one pin of EXOR gate dedicated to positive as logic 1, and other pin connected to the input binary bit, then output of EXOR will be swapped by 1’s with 0’s and 0’s with 1’s. At the same time other advantage is if the dedicated input pin is given logic, then out put will be same as input binary code.

Such that in that whole circuit by changing selective pin as 0 logic it works as adder and by changing selective pin as 1 logic it works as subtractor’s 1’s compliment input.

Let we consider A + B it is a simple addition,

For

A – B = A + (- B) = A + (B 1’s compliment + 1)

= A + B 1’s compliment + 1

As shown above to find A – B we give the full adder inputs as a to A, b to B 1’s compliment and finally c in as positive logic 1. Thus adding 2 bits of A And B in this way we get A- B.

For the another stage of bit like 2 to 4 bit subtraction is as simple like addition just feeding the carry to next bit stage of carryin full adder. Such that the rippling of carry gives subtracted binary code of all input bits.

Now lets consider this for 4-bit subtractor* in cla logic.

As shown above the negative bit input takes through EXOR gate. Make sure selective pin as logic 1 as well carry in as well set to logic 1. Such that we can construct a 4-bit parallel CLA subtractor*. Where A0 to A3 are A inputs and B0 to B3 are B inputs and S0 to S3 are sum outputs and final carry output is C4.

When considering the D flip-flop input, IC pins will be extra adder as flip-flop inputs D and clock and its out put pins Q and QN, where Q is primary usage port. At each combination of bit level addition or subtraction extra ports added such that to obtain C1, C2 and C3.

As expressed above we construct a single 4-bit parallel cla adder/subtractor* by just selecting proper selective mode and input carry logic.

In further assessment of more than 4-bit parallel adder/subtractor*, there is no need to give cin as dedicated logic 1 but just feed it to the next stage input.

Similarly in serial adder mode after just passing half pulse of input need to be set cin to logic 0, such the before the feed-backed carryout of serial adder superimposed each other.

But up to my project developed a 4-bit test subtractor* to study the characteristics of a subtractor but it can deliver great adder/subtractor* applications when it used as proper set of selective pin with respect to cin pin.

This not only just a dedicated 4-bit adder / subtractor*, we developed in a way that we can use this in 1 to 4 bit either adder or substractor functionality. Even in bit mode or serial mode or parallel mode by choosing a proper flip-flop functionality. Thus it will be a best test adder at any stage of application as it works in any mode of development.

This adder/subtractor* is a fast functioning as a dedicated CLA adder but the gates we used to develop total architecture are not used all time in all application, that leads to a bit of waste power dissipation at not used part of circuit. But it is not a problem as its speed is good and at testing stages its wide application.

Thus we developed this CLA adder/subtractor* at different stages for such dedicated IC applications. The architecture for CLA adder/substracor* will shown below.

The developed IC design in mentor graphics modified C4 and XOR logic as before. They are developed using NAND gate logic thus we obtain great speed and efficiency. In the final stages the static errors will be reduced by padding inside IC design such that we reduce the blurs in the out put signals. Where using fast universal NAND gate implementation is one of better applied IC design.

Such that we implemented some own logics while developing such a fast and much efficient is main motto of research.

7. Conclusion:

In the project of CLA Adder we obtained the knowledge about the functionality of adders and developed a fast adder using CLA Logic. We even obtain the knowledge about CMOS technology and functionality of IC Gates. As we developed using NAND gate logic implementation the architecture of IC will be much faster and efficient.

From the obtained results of CLA waveforms and IC design by comparing the theoretical and practical values are verified each other. Such that I can conclude the developed IC’s are well functioning in any application era.

Finally we can conclude that a 4-bit CLA logic is developed in Conventional, NAND gate architecture and Adder/Subtractor* architectures IC design and layout of IC design obtained and verified without errors. Functional and Electric Characteristics studied similar to CMOS technology as they developed.

Tested at several combinations of input signals at different variety modes of IC applications.

8. Reference:

BOOKS:

1. Digital integrated circuits analysis and design BY JOHN E. Ayers.

2. Digital integrated circuit Design by HUBERT KAESLIN.

WEB pages:

1. logic gates retrieved form- www.antonineeducation.co.uk/Electronics_AS/Electronics_Module_1/Topic_2

2. http://www.cse.dmu.ac.uk

3. http://www.depi.itch.edu.mx/

4. http://www.mashhadkit.com/2004/Learning/logic.htm

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8. http://www.freepatentsonline.com/3887134.html

9. http://www.freshpatents.com/Size-conscious-hose-clamp-

10. http://www.faqs.org/patents/app/20090108472

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Appendix

Abstract 1

1. Introduction 2

2. Background 3

2.1 Adder 3

2.2 Subtractor 3

2.3 Half adder 4

2.4 XOR gate 4

2.5 Full adder 5

2.6 Serial adder 7

2.7 D Flip-flop 8

2.8 Parallel Ripple Carry adder 9

2.9 Carry look-ahead adder 10

3. 4-bit CLA adder developed in Conventional logic 10

4. 4-bit CLA adder developed in NAND gate 13

4.1 CMOS logic 17

4.2 NAND logic 18

4.3 NOR logic 19

4.4 Why NAND gate is best universal gate 19

4.5 4-bit CLA adder developed in NAND gate 22

4.6 Serial adder with CLA logic 23

4.7 Ripple carry adder with CLA logic 24

5. 4-bit CLA adder/subtractor* logic developed using NAND gate. 25

6. Results Wave farms and examples Layouts

7. Concussion 28