Series Pass Voltage Regulator From Discrete Electronic Engineering Essay
The objective of this project was to construct and design a 9V ± 0.3V, 1A series pass voltage regulator from discrete electronic parts. The voltage regulator must exhibit a voltage regulation of 5% or better and should be supplied with a dc input voltage. The regulator circuit was required to include a way to disconnect the load from the regulator if the load current exceeded 1A or if the temperature of the series pass element exceeded 40°C.
It was necessary to measure each parameter of the circuit and convert it from an analog to a digital signal. This signal would provide data necessary to display the values on the Spartan III FPGA Development Board.
The numerical display was not to have any zeros leading a number, unless it affected the value. Also, the display was to be cyclic, alternating at 5 second intervals.
The circuit was designed, built and tested. It produced 9.03V output and 1.02A through a 9Ω load. The cut-off protection worked as well as the variable sensing circuitry. The linkage of the analog and the digital components, however, remain incomplete.
Contents
LIST OF FIGURES
LIST OF TABLES
LIST OF ABBREVIATIONS AND SYMBOLS
Symbol
Description
ADC
Analog to Digital Converter
Op-amp
Operational Amplifier
V
Voltage/Volts
I
Current
R
Resistance
A
Ampere
Ω
Ohm
°C
Degree Celsius
F
Farad
IC
Collector Current
IB
Base Current
VBE
Base-Emitter Voltage
LUT
Look Up Table
BCD
Binary Coded Decimal
MUX
Multiplexer
CLK
Clock
DPDT
Double Pole Double Throw
FPGA
Field Programmable Gate Array
Table : List of Abbreviations Contained in this Report
INTRODUCTION
Commercial power is usually distributed with an AC supply. An unregulated voltage such as this could cause damage to many household appliances and electronic devices. Therefore it is a safety hazard.
A voltage regulator is a device that maintains a relatively constant output voltage for a varied input voltage. It functions by comparing the output voltage to a fixed reference and minimizing this difference with a negative feedback loop.
The aim of this project to design a series pass voltage regulator with an output of 9 ± 0.3V and regulation of at least 5%. It should be able to disconnect the load from the regulator for temperatures exceeding 40â°C and a current greater than 1A.
Using A/D converters, these values (output regulator voltage and current, temperature of the series pass transistor) were converted to digital format and displayed on the Spartan III FPGA Development Board.
Each value received from the analog component should be displayed with no unnecessary leading zeroes. The display had to alternate between different variables of voltage, current and temperature.
The Digital Component of this project was designed in Xilinx ISE 7.1i, and the necessary tests were carried out. A User Constraints file was created, which allowed for the programming of the FPGA Board.
BACKGROUND THEORY AND LITERATURE REVIEW
Using an unregulated power supply is unfeasible for most tasks. This is because as the load current increases, the ripple voltage increases and the DC output voltage decreases. The voltage regulator greatly reduces ripple and produces a steady output voltage for a range of input voltages.
Different types of voltage regulators have different functions. There are two main types, shunt and series voltage regulators.
Shunt Voltage Regulator
For a shunt voltage regulator, the regulating device is placed in parallel with the load. A resistor is placed in series with the load and the unregulated supply. The current is varied through the control element depending on the load current. This causes a voltage drop across the resistor in series, maintaining a constant load voltage. (Prof. Gift, 2012)
Figure : Shunt Voltage Regulator
Shunt Voltage Regulator Example: Zener Diode Regulator
Figure : Zener Diode Voltage Regulator
The zener diode is a semi-conductor diode designed to operate in the reverse-biased region. In forward bias, it functions as a normal diode but when in reverse bias, it breaks down for voltages exceeding the breakdown voltage, or zener voltage. For operation in this region a current Iz is required where the limits being the minimum and maximum current for the diode to operate without breaking down. (Prof. Gift, 2012)
Series Voltage Regulator
For a series voltage regulator, the regulating device is placed in series with the load and the unregulated supply. (Prof. Gift, 2012) The output voltage is sampled by a circuit that provides a feedback voltage to be compared to a reference voltage. If the output voltage increases, the comparator circuit provides a control signal to cause the series control element to decrease the amount of the output voltage, thereby maintaining the output voltage. If the output voltage decreases, the comparator circuit provides a control signal to cause the series control element to increase the amount of the output voltage. (Electronic Devices and Circuit Theory 7th Ed.)
Figure : Series Voltage Regulator
There are different circuit topologies for the series voltage regulator. These will be examined next.
Simple Series Transistor Regulator
To improve the current capacity of the zener diode regulator, a transistor is used in the emitter follower configuration. This acts as the series control element. The collector is supplied by the regulated voltage. The transistor reduces the load current capacity of the zener by a factor of the transistor current gain. The zener voltage is therefore produced at the emitter. The equation IC = βIB is used to link the collector current and the base current. Due to high current gain, even very large changes in IC result in only small changes in IB. This means IZ is mostly stable. The input voltage must be greater than the diode voltage to ensued proper transistor bias. (Prof. Gift, 2012)
Figure : Simple Series Transistor Voltage Regulator
IZ – current through the zener diode
IC – collector current
IB – base current
Discrete Voltage Regulator
A transistor Tr2 is connected as the series pass transistor and another one Tr1 acts as the error amplifier. In the single transistor regulator output ripple voltage is low, but the output voltage still varies. This is due to the VBE/IC characteristic of the transistor. Feedback is used to correct the output. This amplifier compares the sampled voltage with a reference voltage in order to generate a signal proportional to the difference. This is used to drive the series pass element, which then varies the output voltage such that the error is reduced and the output voltage regulated.
Figure : Discrete Transistor Voltage Regulator
The voltage across the series element is (Vin – Vout). The input voltage to the error amplifier is βVout – Vref, where .
The output voltage across the series element is an amplified version of the input voltage,
. If Vref is constant, . This is the stability factor.
This means that the ripple voltage is reduced by a factor of . The higher the loop gain, Aβ, the better the regulator performance. ‘A’ is gain of error amplifier.
The resistor R can be connected to the regulated side of the circuit to improve the design and decrease ripple voltage. Also, a capacitor may be placed in parallel to the Zener diode. Another capacitor can be placed across the output removing output noise and input impedance at high frequencies. A Darlington Pair may be used as the series element. This has two transistors in a single package. The Darlington Pair increases the current gain of the series element, making it able to supply a larger load current if required. (Prof. Gift, 2012)
Operational Amplifier Series Voltage Regulator
In order to improve the regulator performance, the loop gain A is increased. A simple method of doing this is to replace the transistor error amplifier with an operational amplifier as shown in figure 6. The operational amplifier compares the reference voltage of the zener with the feedback voltage sampled by resistors R1 and R2. The Darlington Pair design is used here and R3 connected to the regulated supply to reduce the ripple voltage. The operational amplifier (op amp) must be supplied by the unregulated input voltage. (Prof. Gift, 2012)
Figure : Operational Amplifier Series Voltage Regulator
STANDARDS
Certain standards were considered in the undertaking of this project. These are:
ISO 9001:1994 – Quality Systems – Model for Quality Assurance in Design, Development, Production, Installation and Servicing (http://www.ttbs.org.tt/)
TTS 620 2008 – Occupational Safety and Health Risk Assessment Requirements(http://www.ttbs.org.tt/)
BS QC 790304:1994 – Specification for harmonized system of quality assessment for electronic components. (http://www.standardsuk.com)
RISK ASSESSMENT
Possible Hazards:
15V supply voltage. Risk of electrical shock, burns and death.
Solder fumes present. Dangerous if inhaled.
The heat generated by the power resistor could cause burns.
The tip of the soldering gets very hot and could cause severe burns or start a fire.
Clipping wires and leads may cause them to be projected into eyes and face.
Steps Taken to Avoid Risk:
Ensured that student was properly grounded. Proper clothing and footwear were worn. No long hanging jewellery or hair.
Before energising a circuit, it was checked by a technician.
Tested conductors before handling them.
Exhaust fan present in lab. Regularly stepped outside for fresh air.
Clipped wires away from face of anyone present.
DESIGN APPROACH AND METHODOLOGY
Project Requirements:
Design and build a 9V ± 0.3V, 1A Series Pass Voltage Regulator using discrete electronic components.
Regulator must have a voltage regulation or 5% or better and must be fed by a dc input voltage from a laboratory power supply. In addition, the regulator must incorporate temperature and over current sensing circuits which would disconnect the load from the regulator, for temperatures and currents exceeding 40 degrees centigrade and 1 A respectively.
The output regulator voltage and current, together with the temperature of the series pass transistor must be converted to digital format using A/D converters and displayed on the Spartan 111 FPGA Development Board when selected. The following specifications must be met for the display of the variables:
1. The units of all variables are to be displayed along with the respective reading.
2. The voltage is to be displayed to 1 decimal point.
3. The current is to be displayed to 2 decimal points.
4. The temperature is to be displayed as a whole number.
5. The display of the readings for voltage, current and temperature are to automatically appear in a cyclic manner, with each reading being displayed for 5 seconds.
6. All leading zeros are to be suppressed. (ECNG 2004 Design Project Description)
This design had both an analog and a digital component.
ANALOG COMPONENT
This component involved the design and construction of the Series Pass Voltage Regulator and the sensing circuitry to detect current, voltage and temperature. These sensors were constructed to relay the values necessary for the digital component. Analog to Digital Converters were designed to convert the analog output from the current, voltage and temperature sensing circuits to digital format so as to be to be read by the Spartan FPGA Board.
Design of the Operational Amplifier Series Voltage Regulator
Figure : Circuit Diagram of the Operational Amplifier Series Voltage Regulator
The regulator was powered by a DC input voltage from a laboratory power supply.
The voltage used in the design process for the purpose of calculation was 15 volts.
Choosing the Zener Voltage and Zener Current
The Zener Voltage, Vz was supplied by the Zener Diode, D1 as shown in Figure 7 above. The Zener Voltage was used as a reference voltage by the Operational Amplifier. The op amp is functioning as a differential amplifier in this situation. The difference between the inputs at the inverting and non-inverting terminals is amplified.
Gain,
The output voltage, VZ – zener voltage
Vz should be high enough so that gain would not decrease to achieve the required output.
If Vz was too high, i.e. the output voltage, no current would flow through D1. An appropriate value between 0V and 9V was chosen, VZ = 4.8V.
The IN4732 Zener Diode was chosen and the specification sheet for this model was obtained. The specified test current was 53mA, and the chosen value was 40mA. This was chosen to ensure proper bias.
Calculating Resistor R3
The resistor R3 was in series with the Zener Diode. Therefore, the current through them is the same.
A 100 Ω resistor was chosen as it was the closest one in value available in stores.
R3 = 100Ω
Calculating Resistors R1 and R2
Resistors R1 and R2 formed a potential divider providing the inverting input of the op amp. This sampled the output and sent it to the error amplifier. If the value of the output changed from the designed, the voltage drop across the resistors would change and the op amp input voltage would change, producing an error voltage at the output of the op amp. This error voltage will either turn on more or turn off more Transistor Tr1 and effectively Tr2 as well.
The output voltage, Vo is related to the Zener Voltage by the equation below.
Substituting Vo = 9V and Vz = 4.8V,
Therefore,
If R2 chosen to be 10kΩ, then
Therefore, R1 = 8.8kΩ and R2 = 10kΩ.
Choosing an Operational Amplifier
The LF351 op-amp was chosen for this design. It only needed to function as a differential amplifier.
Choosing the Series Pass Transistor
The required output current was 1 Ampere. Therefore the maximum collector current of the series pass transistor had to be greater than 1 A. high power transistor was needed, but the current gain of power amplifiers is low (approximately 40). The base current and collector current for a transistor are related by the following expression.
Substituting Current gain, hfe = 40 and Ic = 1 A,
The LF351 op amp could not supply this base current. A Darlington Pair arrangement was used instead. Darlington Pairs have high current gain. The high power transistor chosen was TIP31C, packaged in a TO-220 Case. The current gain, hfe1 of this transistor was specified to be between 10 and 50, so a value of 30 was used.
An NPN medium power transistor, BFY51 in a TO-39 metal package, was chosen for Tr2 in Figure 6. The current gain, hfe2 was found to be 123.
Hence, total current gain of the Darlington Pair:
hfe1 Ã- hfe2, i.e. 30 Ã- 123 = 3690.
Substituting Current gain, hfetotal = 3690 and Ic = 1 A,
Design of the Voltage Sensing Circuit
The purpose of the Voltage Sensing Circuit was to determine the output voltage of the regulator and relay this voltage to the Analog to Digital Converter input. The Analog to Digital Converter (ADC) chip (ADC08040 IC) had a reference voltage of 4.5V. The maximum voltage possible was 9.5V. Hence if the voltage output was 9.5V, the ADC08040 input voltage should be 4.5V.
VO had to be stepped down by a potential divider before it could be sent to the ADC08040. It was stepped down by a factor of .
Let R1 = 1kΩ, then R2 = 1kΩ
This voltage was sent to a Unity Gain Voltage Follower (Figure 8) and was input to the ADC circuit. (Prof. Gift, 2012)
Voltage Sensor.bmp
Figure : Voltage Sensing Circuit
Design of the Current Protection Circuit
The purpose of this was to disconnect the load from the regulator when the current flowing through the load surpassed 1A. The protection circuit monitored the load current and sent a signal to a device to disconnect the load, when the current rose to over 1A. A 1Ω shunt was used in series with the 9Ω load resistor. The shunt voltage was used to determine cut-off.
An instrumentation amplifier was chosen (INA114AP) to compare the temperature sensor voltage and a potential divider voltage. The shunt voltage was amplified to increase chances of accurate determination of when to disconnect the load. A potential divider was constructed to deliver a4V, and the shunt voltage was also amplified to 4V.
Potential Divider:
Which gives:
Let R1 = 20kΩ
The voltage from the shunt was amplified to 4V as well, and this was done by an op-amp and two resistors set up in the non-inverting amplification configuration shown below. The reference used to be amplified was 0.9V from the shunt, as this was the value which, if exceeded, cut-off and disconnection of the load was supposed to occur.
For an non inverting amplifier,
Vo = 4V, Vi = 0.4V,
And
Let R1 = 2.4kΩ, R2 = 8.2kΩ
.Temperature Amp Input to INA.bmp
Figure : Circuit for Comparison and Determination of Cut-off
When both inputs have the same voltage across them, the instrumentation amplifier would have an output of zero. The transistor in Figure 10 would be turned off and the base would be at 0V.
The transistor used was a 2N3904 (Ic = 200mA). If the output is non-zero, the base would be driven by a voltage and the transistor will be “ON”.
When the output is zero (same inputs) the transistor would be “OFF” and the relay coil would be grounded through the transistor. Current would flow through the coil, producing a magnetic field, and the relay would latch.
When the instrumentation amp inputs are different, the output would saturate at +Vcc, i.e. 9V. The coil would an equal voltage at either end and so would have no voltage drop across it, meaning no current flowing through it. The relay is effectively OFF. There is a Normally Open (N.O.) Switch between pins 2 & 3, and 7 & 5 of the relay as well as Normally Closed (N.C.) Switches across pins 2 & 3 and 7 & 6. The N.O. switches close and the N.C. switches open when the relay latches. The load was connected across the N.C. pins. When the instrumentation amp has the same inputs, (zero output), and there is a voltage drop across the coil, current flows and the relay latches, disconnecting the load from the circuit.
The relay had a rated voltage of 6V and the coil had a measured resistance of 70.5Ω. The relays, however, were actually found to latch at a voltage of 3.2V. Therefore for calculation purposes 3.5V is used = 49.6mA was needed to latch the relay.
A potential divider was used to provide the required voltage for the relay.
For a resistor R3,
This caused a voltage drop across the coil, larger enough to activate the coil when necessary.
The voltage across resistor R3 is given by,
For Ic = 49.6mA,
The Base Current of the transistor is given by
For Ic = 49.6mA, and hfe = 100,
To bias the base of the transistor for the 9V output of the op-amp,
A 16kΩ resistor was used. This would change VBE of the transistor. The new VBE was well within the operating range required for the resistor.
Temperature Cutoff.bmp
Figure : Current Protection Circuit
Design of the Current Sensing Circuit
The Current Sensing Circuit determined the voltage regulator output load. This value of current would be received by the ADC input. The ADC chip (ADC08040 IC ) was 4.5V. The Current LUT could convert a maximum of 1.29A. This means when the regulator reaches 1.29A, the ADC will be at 4.5V.
A 1Ω shunt resistor was placed in series with the load. The 9V regulated output would now be applied to a combined load of 10Ω.
Voltage drop across the shunt:
Therefore:
The output voltage across the shunt is 0.9V. This will correspond with the maximum voltage which will give all 1’s at the ADC output. Thus the voltage must be stepped up using a non-inverting op-amp. The voltage of 0.9V was stepped up to 4.5V.
This means the gain is = 5
Let R1 = 2k Ω. Therefore, R2 = 8kΩ
The potential divider voltage was passed through the amplifier and then input into the ADC.
Current Sensing Circuit.bmp
Figure : Current Sensing Circuit
Design of the Temperature Protection Circuit
This disconnects the load from the regulator when the temperature of the Power Transistor (TIP31C) reached 40°C. The Power Transistor temperature was monitored and at 40°C, a signal would be sent from the circuit to a device, disconnecting the load.
The LM35DZ was chosen. Its sensitivity was 10mV/°C. At 40°C, the temperature sensor output would be 0.4V.
An instrumentation amplifier (INA114AP) was chosen to compare the temperature sensor voltage and the potential divider voltage. For a more accurate determination of the load, the temperature sensor output voltage was amplified. The potential divider delivered a voltage of 4V, and the sensor output voltage was also amplified to 4V.
Therefore:
Let R1 = 20kΩ
An op amp and two resistors were used to build a non-inverting amplifier in order to set the temperature sensor voltage to 4V. The reference voltage was 0.4V, since it is at this point cut-off should take place.
For a non-inverting amplifier: , ,
Let R1=1kΩ and R2=9kΩ,
Temperature Amp Input to INA.bmp
Figure : Amplifier Circuit for Comparison and Determination of Cut-off
.
When both input voltages are the same, the amplifier output would be 0V, turning off the transistor. (No VBE present). A 2N3904 transistor was used (Ic = 200mA), so the current would be large enough to latch the relay.
If the amplifier output is not 0V, there would be a voltage drop across the base and the transistor would be “ON”.
When the amplifier output is 0V, the transistor would be “OFF”, grounding the relay, causing current flow in the coil, latching the relay. When the amplifier inputs are at different levels, the output saturates at +Vcc = 9V. Equal voltages exist at both ends of the coil, so no current flows hence the relay is “OFF”. A Normally Open (N.O.) Switch exists across pins 2 & 3, and 7 & 5 of the relay. Normally Closed (N.C.) Switches exist across pins 2 & 3 and 7 & 6. The N.O. switches close and the N.C. switches open upon latching. Consider this load connected across the N.C pins and the amplifier has equal inputs. The amplifier output is 0V, causing a voltage drop across the relay coil, causing current flow and latching of the relay. It follows then that the load is disconnected from the circuit.
For a resistor R3,
R3 was used to activate the coil by creating a voltage drop across it.
For Ic = 49.6mA,
For biasing,
A 16kΩ resistor was used instead.
Temperature Cutoff.bmp
Figure : Temperature Protection Circuit
This circuit was designed to relay the temperature of the power (TIP31C) to the ADC input. The ADC chip (ADC08040 IC ) reference voltage was 4.5V. The Temperature LUT could convert up to 129â°C. At this temperature, the ADC should be 4.5V. A Temperature Sensor (LM35DZ) in a TO-92 package used to determine the temperature. This had a sensitivity of 10mV/°C. At 129°C, VO = 1.29V.
Sensor output voltage was stepped up using a non-inverting op amp by a factor of
, Let R1 = 1k Ω. R2 = 2.49kΩ ≈ 2.5kΩ
The sensor voltage was amplified and input into the ADC.
Temperature Sensing Circuit.bmp
Figure : Temperature Sensing Circuit
A copper strip board was used to build the voltage regulator circuit since the solderless breadboard could only take up to 0.5A.
Inputs: Voltage Supply of 15V Outputs: Voltage Sensing Output
OV Ground Regulated 9V Output
Temperature Sensing Voltage
A voltage follower was used to buffer the output. The circuit was constructed as seen in figure 15:
Figure : Complete Sensing and Cut-off Circuit
DESIGN OF THE ANALOG TO DIGITAL CONVERSION CIRCUIT
An 8 bit representation was used with reference to the 4.5V signal. The analog signal was converted to a digital signal from the 3 sensing circuits using the schematic shown below. Analog to digital conversion was done using the. A resistor pack was used to provide over current protection. This circuit was built and tested for each of the three sensing circuits. A combination of LED’s was used for the input of the analog voltage. AD Converter Circuit.bmp
Figure : Schematic for ADC control configuration
Op amps were used to buffer the inputs. The outputs were mapped onto the respective pins of the 40-pin IDE cable used to interface with the Spartan III Board.
Figure : 40 Pin Expansion Connector (Spartan III Toolkit Datasheet)
Data was transmitted using these pins to the ADC.
DIGITAL COMPONENT
The FPGA board was programmed so as to use the Seven Segment Display. Xilinx ISE 7.1i was used to design and construct the display for all the variables.
Design of the Basic Display Unit
Multiplexers, Frequency Dividers, a Look up Table Device and a Binary Coded Decimal to 7-Segment Converter were used to create the Display Unit.
The 16-bit 3×1 Multiplexer
Multiplexers may have more than one input but usually have one output. A combination of numbers is assigned to each input pin. Using these combinations, the respective input data is sent to the output pin. Therefore the bits that are chosen which input data set to display. In this design, two multiplexers were used, a 4-bit 4×1 and a 16-bit 3×1 multiplexer. 3×1 means 3 data inputs, 16- bit means each input is of 16 bit capacity.
16bit3to1muxschem.bmp
Figure : Schematic Diagram of a 16-bit 3 to 1-line Multiplexer
The 4-bit 4×1 Multiplexer
The 4-bit 4×1 multiplexer can handle up to four combinations of inputs. To select which input is displayed, two bits are necessary. The output was a bus of width 4 bits. It split the 16 bit output into four sets of 4 bits. The 4-bit 4×1 multiplexer is shown in figure 19.
4bit4to1mux.bmp
Figure : Schematic Diagram of a 4-bit 4 to 1-line Multiplexer
Binary Coded Decimal (BCD) to 7-Segment Display Unit
The BCD unit accepts four bits of data, e.g. D3D2D1D0, and determines which segments of the 7-segment display to turn on and off so as to represent the value of the input data. Figure 20 shows a 7-segment display. This type of display is common in electronic equipment e.g. calculators, microwaves, digital clocks. The Minimum Expressions for the BCD are:
Seg_a = D’3D’2D’1D0 + D2D’1D’0 + D3D2 + D3D1
Seg_b = D2D’1D0 + D2D1D’0 + D3D2 + D3D1
Seg_c = D’2D1D’0 + D3D2 + D3D1
Seg_d = D’2D’1D0 + D2D’1D’0 + D2D1D0 + D3D1 + D3D2
Seg_e = D0 + D2D’1 + D3D1
Seg_f = D3D2 + D’2D1 + D1D0 + D’3D’2D0
Seg_g = D3D2 + D3D1 + D2D1D0 + D’3D’2D’1
For each expression, logic gate circuits were created. Each segment was then used to build the final BCD to 7-Segment Converter. The combinations of segments that would form the values were organised.
The Look-Up-Table (LUT)
This was used to determine which display unit anodes were to be turned on and off. There were four individual 7-segment displays. Each one had its own anode and as such could be controlled by choosing the anode of the respective display.
lut.bmp
Figure : Schematic Diagram of a Look-Up-Table (LUT)
Modulo 4 Counter
The Modulo 4 counter was used to perform automatic cycling of the anodes to be displayed. Only one anode was on at a time for each different combination.
Moduloo4counter.bmp
Figure : Schematic Diagram of a Modulo 4 Counter
For multiplexed displays, the entire display is not lit up as the same time. The characters are made up of segments which, under certain conditions, become active. Each character is displayed one at a time. Switching of characters takes place so fast it appears that all the displays are on at the same time. The speed of switching is called the frequency divider (in this case 1kHz). This activates the modulo 4 counter which causes the LUT to choose one of four inputs to be chosen from the 4-bit 4 to 1 multiplexer to send to the 7 segment display.
The Combined Display Unit
Data Unit.bmp
Figure :Schematic Diagram of the Display Unit
Upgrade of the Display Unit to display the Decimal Point
The LUT controls the switching of the anodes on the four 7 segment displays. Each 7 Segment Display has a decimal point that can be turned on or off if necessary. This was necessary in this project when displaying voltage and current.
For a voltage, the decimal point is on the 3rd anode, a2.
9.
V
For a current, the decimal point is on the 4th anode, a3.
0.
9
9
A
This means that the point will only be on when S0 and S1 select to display voltage or current, and when the third or fourth anodes are on respectively.
The Essential Prime Implicants were chosen from a truth table and the minimized expression was produced as follows:
The Logic Gate circuit was constructed as shown below and implemented in Xilinx ISE 7.1i. A Macro was then created and connected appropriately in the Updated Display Unit Schematic.
Decimal Point Upgrade.bmp
Figure : Logic Gate Circuit for Decimal Point Upgrade
Upgrade of the Display Unit to display the Units for each Variable
The Display Unit was upgraded a second time in order to allow the units of each parameter to show
Parameter
Unit
Symbol for Unit
Voltage
Volts
V
Current
Amperes
A
Temperature
Degrees Celsius
â°C
Table : Parameters to be Displayed and their Respective Units
The BCD Converter had to be updated to ensure when certain select bits were chosen, the segments would align to form the unit symbol on the first anode.
Since there are four select inputs, D3D2D1D0 , there are 16 possible combinations of these bits forming different outputs. 0000 to 1001 in binary form represents 0 to 9 in decimal form. This means that there are combinations 1010 to 1111 to choose from to display a unit. 1101 was chosen for voltage, 1110 for current and 1111 for temperature.
Figure : Common Anode Method of Displaying Characters
The combinations of segments to form the display values were organised and a truth table created. bcd dIDPLAY.bmp
Figure : Segments Used to Display Data
K-Maps were created for each segment to be displayed and their minimized logic equations were derived. The Logic Gate Circuits for each segment were created and were used to form the new Binary Coded Decimal Converter.
A macro was created of the new Binary Coded Decimal Converter which then replaced the older Binary Coded Decimal Converter.
Upgrade of the Display Unit for Automation of the Display
The third display unit upgrade enabled cycling of the display for voltage, current and temperature. There was a 5 second interval set between each display.
If three combinations of select bits were used to represent the parameters, it is possible to display each one when their respective select bits were chosen.
A Modulo Three Counter was used to do this feature. The Modulo Three counter counts from 0 to 2, and outputs each iteration in binary form. Voltage was assigned 00, the first output, current to 01 and temperature to 10.
A frequency divider controlled the time duration of each display and also provided the clock cycles for the modulo 3 counter.
Frequency is
where T = period of the signal.
For a period of 5 seconds,
The input signal used for the modulo 3 counter was 0.2 Hz.
For a n modulo counter,
The Spartan Board had a clock signal of 50MHz, from the specification sheet.
Reference frequency = 50MHz, Desired frequency = 0.2Hz,
A modulo 125000000 counter would have to be created to provide this timing function.
This was not feasible.
1kHz signal was also present, being used to drive the display unit.
Reference frequency = 1kHz, Desired frequency = 0.2Hz,
A module 2500 counter was created to count from 0 to 2499 and reset. (0000 0000 0000 to 1001 1100 0011). This output from this counter was transmitted to the 16bit 3×1 Multiplexer.
Upgrade of the Display Unit for the Suppression of Leading Zeros
The fourth upgrade concerned the suppression of leading zeros. This suppression affects the 4th anode when voltage is displayed and affects the 4th anode when displaying temperature. The 3rd anode is also affected when displaying temperature if the value is less than 10°C.
As a result of this, the following values will be checked before displaying them to check whether or not they are all zeros:
Voltage – Bits (15:12) anode a3
Temperature – Bits (11:8) anode a2
Temperature – Bits (15:12) a3
The 3rd anode will only be suppressed the values of bits (15:12) and bits (11:8) for temperature are zeros.
Supression of Zeros.bmp
Figure :Logic Circuit used to Suppress Leading Zeros
For temperature, the circuit checks if the values of both anode 3 and 4 are zero. If so, they both will be turned off. If the 3rd anode is a zero only, neither will be turned off. If the most significant bit of temperature is zero but the value of the third anode is non-zero, the fourth anode will turn off alone. Since there were only three inputs so the 1 bit 3×1 multiplexer was chosen.
The Upgraded Display Unit
The Upgraded Display Unit (Figure 27) consists of all the required upgrades.
This Display Unit has a clock input, a reset input, three 12 bit inputs for data entry and three 4 bit inputs for display purposes. The outputs are 7 bit segments, 4 bits to the anodes and even a Decimal Point output.
Final Display Unit 1.bmp
Figure : The Upgraded Display Unit
Design of the FPGA Components
The FPGA or consists of the upgraded Display Unit , a 1kHz Frequency Divider and the Voltage, Current and Temperature LUT’s. These allow 8 bits to be inputted, and convert the 8 bit number to a 12 bit number, which is then transferred to the Display Unit. This 8 bit number was received from the ADC.
The 1kHz Frequency Divider set the time for the powering on of each anode.(For 1 ms at a time)
FPGA Components 1.bmp
Figure : FPGA Components
Interfacing with the Spartan III Board
The pins to be used for data transmission from the ADC circuit were determined by the Spartan III Toolkit Datasheet. Twenty-four (24) had to be selected from one connector. Connector A2 was chosen. The table below shows the chosen pins of Connector A2 and their pin number.
Output bit from ADC Circuit
FPGA Pin
Connector Pin No.
Vv0
D5
5
Vv1
D6
7
Vv2
E7
9
Vv3
D7
11
Vv4
D8
13
Vv5
D10
15
Vv6
B4
17
Vv7
B5
19
Vc0
B6
21
Vc1
A7
23
Vc2
A8
25
Vc3
B10
27
Vc4
B11
29
Vc5
A12
31
Vc6
A13
33
Vc7
E6
4
Vt0
C5
6
Vt1
C6
8
Vt2
C7
10
Vt3
C8
12
Vt4
C9
14
Vt5
A3
16
Vt6
A4
18
Vt7
A5
20
Table : Chosen Pinout for A2 Expansion Connector
Twelve pins were chosen from Connector A1.These were set as either PULLUP or PULLDOWN, in order to allow display of the units.
Output bit from ADC Circuit
FPGA Pin
Pin Value
Unit Displayed
VUnit0
F3
PULLUP
V
VUnit1
E3
PULLDOWN
VUnit2
G5
PULLUP
VUnit3
H4
PULLUP
IUnit0
L5
PULLDOWN
A
IUnit1
N3
PULLUP
IUnit2
M4
PULLUP
IUnit3
M3
PULLUP
TUnit0
F4
PULLUP
C
TUnit1
E4
PULLUP
TUnit2
H3
PULLUP
TUnit3
J4
PULLUP
Table : Chosen Pinout for A1 Expansion Connector for Display of Units
The other FPGA Pins necessary for proper operation of the Digital Component are shown in the table below.
Design Port
FPGA Pin to be mapped to
clk
T9
reset
M13 (pushbutton)
anode(0)
D14
anode(1)
G14
anode(2)
F14
anode(3)
E13
seg(0)
E14
seg(1)
G13
seg(2)
N15
seg(3)
P15
seg(4)
R16
seg(5)
F13
seg(6)
N16
Table : Pin Configuration for the FPGA Component Unit
RESULTS
Voltage Regulator
Two test were carried out on the voltage regulator, a full and no load test. The current through the load and the output voltage was measured and tabulated.
Condition
Parameter
Expected Output
Actual Output
NO LOAD
Voltage
9.00V
9.03V
Current
—-
—-
FULL LOAD (9Ω)
Voltage
9.00V
8.70V
Current
1.00A
1.02A
Table :Results for Voltage Regulator
The regulator was design within the requirements, to produce 9V± 0.3V at 1A.
The percentage regulation designed for is within the required range of 5% or better.
Sensing Circuits
Voltage Sensing
The output voltage of the regulator was produced by a voltage sensing circuit. The maximum voltage chosen was the out voltage of the regulator, 9.03V and therefore the out of the voltage sensing circuit should be 4.5V. The hexadecimal voltage of the Voltage LUT was altered to give a reading of 9.03V with maximum input. The value measured was 4.45V.
Current Sensing Circuit
The current passing through the load is represented by a voltage produced by the current sensing circuit. The maximum output current is 1.29 which corresponds to 4.5V. For a 9Ω load, the current through it is 1A, this value corresponds to 3.56V. The value measure was 3.4V.
Temperature Sensing Circuit
A LM35DZ temperature sensor was designed to produce a voltage which correlates with the temperature of the TIP31C transistor. The maximum temperature specified was 129oC which corresponds with maximum voltage out from the voltage sensing circuit. The temperature under no loading is 23oC, which is room temperature; this produces an output voltage of 222mV, which is equivalent to 22.2oC.
Cut-off Circuits
Current Cut-off
Modification to the specifications was needed since the cut-off current circuit was had to switch off when 1A was exceeded. However, the maximum current used is 1.02A. Hence a cut-off current of 1.1A was used. /the load would be disconnected simultaneously with the drop of the output voltage of the INA114AP from 9V to 0V. The value measured was 7.5V.
Temperature Cut-off
The load was also disconnected if the temperature of the TIP31C exceeded 40oC that is 0.4V. This 0.4V was amplified by the INA114AP to give an output 0f 4V. When tested the circuit reached 4.2V or 42oC before disconnecting from the load.
Analog to Digital Converter
A potentiometer and 8 LED lights where used to test the output of the analogy to digital converter which had varying inputs from 0V to 4.5V. The table below showed the results acquired.
Vref/V
Vin/V
8-bit Binary Representation
Answer
4.5
0.0
00000000
4.5
0.4
00010110
4.5
0.8
00101100
4.5
1.2
01000011
4.5
1.6
01011010
4.5
2.0
01110001
4.5
2.4
10001000
4.5
2.8
10011110
4.5
3.2
101100101
4.5
3.6
11001100
4.5
4.0
11100011
4.5
4.5
11111111
Table : Results from Testing of the ADC Circuit
Digital Component with upgrades
Test values were chosen for each parameter in the Implementation constraint file. The Spartan board was programmed using a computer and a series of test where carried out. The results are shown in the table below.
Case
Value to be Displayed
Expected Display
Value Displayed
1
02.0V
2.0V
2.0V
2
05.0V
5.0V
5.0V
3
09.0V
9.0V
9.0V
3
0.01A
0.01A
0.01A
4
1.00A
1.00A
1.00A
5
1.29A
1.29A
1.29A
6
005°C
5°C
5°C
7
010°C
10°C
10°C
8
100°C
100°C
100°C
Table : Results from Testing of the FPGA Components Project
Interfacing of the Analog Circuit with the Digital Circuit
Interfacing the analog circuit to the digital one, some errors where produced. This was due to the sensitivity of the LUT. The LUT produced varying outputs at a time which caused flickering of results; this was due to the LUT swift changing with the corresponding small changes in voltage.
Each sensing circuit gave an output which was buffered to allow it to only transmit data from analog to digital so that the readings were accurate.
DISCUSSION
This project required the design and construction of a series pass voltage regulator with the capacity to produce a 9V ± 0.3V regulated signal and the ability to drive up to 1 Ampere of current through a load.
The voltage regulator was designed simulated using MultiSim 10. It was then implemented using discrete components on a bread board. No load was connected to the output so as to isolate the bus of the breadboard. The voltage regulator design was then built using copper strip board and solder. A metal clip was used as a heat sink, since some components could not withstand the large amount of heat the soldering iron produced .The components were kept safe as the heat was quickly transferred to the clip instead of the delicate components (op amps, transistors). To attach the op amps to the board, sockets were used. A 2A fuse was connected in series with the emitter of the transistor to protect it.
The sensing and cut-off circuitry were designed and implemented and a circuit layout plan was used, due to the large number of components.
The digital component was designed on Xilinx ISE 7.1i and was simulated on ModelSim SE 6.0a. The laboratory exercises were vital to the completion of this project. Bus taps and macros were useful in achieving a neat, operational circuit. Linking the analog and digital components was a very complex task, and was not completed to very high standards due to time constraints and other courses workloads.
CONCLUSION
The objectives of this design project were obtained although the design requirements were not precisely met. A voltage regulator was designed so that it produces 9V± 0.3V at 1A and regulates voltage of 5% or better. The Voltage regulator also incorporated sensors so that the load is disconnected if the temperature exceeds 42oC or the current across the load is greater than 1.1A.
The Design Project was a great learning experience as students were exposed to real life application of simulating and designing circuits while developing essential skills such as soldering and testing.
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