Study On The At89c2051 Microcontroller Information Technology Essay

AT89C2051 is low voltage high performance CM08-8 bit microcomtroller with its flash memory is 2k bytes and it used in PEROM memory .,(programmable and erasable read only memory).Atmel is ad device manufactured high debsity non volatile memory technology which is compatible with industry standard MCS-5instruction set.AT89C2051 is a chip which is called as powerful chip,which contains 8 bit versatile CPU with flash memory and monolitihic chip. AT89C2051 is very high flexible and its cost is very effective solution to many other enabled control applications..

The AT89C2051 provides the following different features: it has2k bytes of flash, RAM is 128 bytes, and it varies 15 i/o lines,two different level of interrupt architecture,serial port(duplex) port,a precision along comparator,on-chip oscillator and clock circuitry.AT89C2051 is deisned with static logic for operation down to zero frequency and support two software which is selectable saving power modewhich steps CPU in idlemode and allowsRAM,timer,serial port and other interrupt system to continue its functioning and the power down mode is disable all other chips but it freezes oscillator .

PIN CONFIGURATION:

PIN DESCRIPTION:

VCC

It functions as Supplying voltage

GND:

It means GROUND

PORT 1:

PORT-1 is an 8-bit bi-directional I/O port .Two pins p1.2 and p1.7 provide internal pull ups.P1.0 and P1.1 require external pull-ups .Some pins serve positive and negative input p1.o and p1.1 as positive input ,of the on chip analog comparator .The port 1 output buffers can sink 20mA and can drive LED displays directly.When 1s are written to port 1 pins,they can be used ad inputs,and pins p1.2 and p1.7 are used as inputs and are extremely low.They will source current because of the internal pull-ups .Port I also receives code data during flash programming and verification.

PORT 3:

Port3 pins p3.0to p3.5,p3.7 are seven bi directional I/O pins with internal pull-ups .P3.6 is hard wired input to the toutput of the on-chip comparator and is not accessible as a general purpose .The output buffers in port 3 and it sink 20mA.High internally being pull ups can be used when 1s are written to port 3.Because of pull-ups input pins port 3 are externallybeing pulled very low..

RST

Reset input.As soon as RST goes high the input pins are reset to 1s.Two machine cycleswhich holds RST pins when the oscillator is running and resets the device.

Machine takes 12 oscillatore or clock cycles.

XTALI

There are input to invert the oscillator and input to internal clock.

XTAL2

Output from the inverting oscillator amplifier.

OSCILLATOR CHARACTERISITICS

XTALI and XTAL2 are the input and output,of an inverting amplifier which can be configured for use as an on chip oscillator. You can use either quartz or ceramic resonator. To drive the device from an external clock source,XTAL1 is driven and XTAL2 should be left unconnected .There are no requirements on duty cycle in external clock signal ,since the input to the internal clocking circuitry is through a divide-by-two flip- f lop, but we can observed minimum and maximum voltage and low time specifications can be observed.

Figure 1. Oscillator Connections

: C1, C2 = 30 pF ??10 pF only for Crystals

= 40 pF ??10 pF only for Ceramic Resonators

Figure 2. External Clock Drive Configuration

SPECIAL FUNCTION REGISTER

The map of the on chip memory area is called special function register space a shown in the table below

Note:In Occupuied not all of the addresses are occupied ,and unoccupied addresses may not be implemented on the chip. Read access to these addresses will being general return

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Inderminate Random data,and write accesses will have not able effect. User software should not be write 1s to these unlisted locations ,since they may be used in future products to invoke new features In that case reset or inactive values of the new bits will always be 0.

Table 1. AT89C2051 SFR Map and Reset Values

RESTRICTIONS ON CERTAIN INTRUCTIONS

AT89C2051 is an very economical and cost effective member of Atmel¿½s growing family of micro controller which containd 2k bytes of flash memory and it is fully compatible with the MCS-51 architecture ,and can be programmed using theMCS-51 instruction set .However there are some considerations one must keep in mind when utilizing certain instructions to program this device.

Jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2k for the AT89C2051.This should be responsibility for the software programmer .For example, LIMP 7E0H should be a valid instruction for the AT89C2051,whereas LIMP 900H would not

BRANCHING INSTRUCTION

LCALL, LJMP, ACALL, , SJMP, JMP @A+DPTR

These conditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall with in the physical boundaries of the program memory size. Violating the physical space limits may cause unknown program behavior.

CJNE […], DJNZ […], JB, JNB, JC, JNC, JBC, JZ, JNZ with these conditional branching instructions the same rule above applies.

For applications involving interrupts the normal interrupt

Service routine address locations of the 80C51 family architecture

Have been preserved.

MOVX-RELATED INSTRUCTIONS,DATA MEMORY

AT89C2051 contain 128 bytes of internal data memory and stack depth is limited to 128 bytes,the amount of available RAM .External data memory access is not supported in this device,nor is external program memory execution .No MOVX[¿½] should be included in the program.80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above.To use to know the physical features and limitations of the device used and adjust the instructions used correspondingly.

PROGRAM MEMORY LOCK BITS

There are two lock bits which can be left unprogrammed(U) orcan be programmed(P) to be obtained the additional features listed.

IDLE MODE

While all the onchip peripherals remain active then CPU puts itself to sleeo in the idle mode and it is invoked in a software.The content of the RAM and all the special functions registers remain unchanged during this mode and it can be terminated by any enabled.

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled.

Interrupt or by a hardware reset. Used, or set to 1 if external pull-ups are used

P1.0 and P1.1 should be set to ¿½0¿½ if no external pullups are used, or set to ¿½1¿½ if external pullups are used.It should be noted that when idle is terminated by a hardware reset,the device normally resumes program execution,from where it left off,up to two machine cycles before the internal reset algorithm takes control.On-chip hardware inhibits access to internal RAM in this event ,but access to the port pins is not inhibited.Write a port pin to eliminate the possibility when idle is terminated by reset,the instruction following the one that involves idle should not be one that writes to a port pin or to external memory.

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POWER-DOWN MODE

The Oscillator is stopped in power down mode and the instruction that involves power down is the last instruction executed .Un till the power down is terminated the on-chip RAM and special function registers retain their values and the only exit is hardware reset. Reset redefines the SFRs but they does not changed the on-chip RAM. Before the VCC is stored in normal operating level the reset should not be activated and must be held active long enough to allow the oscillator to restart and stabilize.

P1.0 and P1.1 should be set to 0 if no external pull-ups are used ,or set to 1 if external pull-ups are used.

INTERNAL ADRESS COUNTER

The AT89C2051 contains an internal PEROM address counter which is always reset to 000H on the rising edge of RST and is advanced by applying a positive going pulse.

ADDITIONAL INFORMATON ABIUT THE AT89C2051

Programming the flash:

The AT89C2051 is shipped with the 2k bytes of on-chip PEROM code memory array in the erased state

Programming Algorithm: To program the AT89C2051, the following sequence is recommended.

1. It has Power-up sequence:

Apply power between VCC and GND pins Set RST and XTAL1 to GND

2. Set pin RST to H Set the pin p3.2 to H.

3.Apply the appropriate combination of H or L logic levels to pins P3.3,P3.4,P3.5 and P3.7 select one of the program operations which shown in PEROM programming modes table to program and verify the array .

4 .Apply data for code byte at location 00H to p1.0 to P1.7.

5. Raise RST to 12v to enable programming.

6. pulse p3.2 once to program a byte in the PEROM array or the lock bits .The byte-write cycle is self timed and typically takes 1.2 ms.

7. To verify the programmed data, lowest RST from 12v to logic H level and set pins P3.3 to P3.7 to the appropriate levels. From the port P1 output data can be read.

8. To program a byte the next address location, pulse XTALI pin once to advance the internal address counter. Apply new data to port p1 pins.

9.Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2k bytes array or until end of the object file is reached

10. Power ¿½off sequence: set XTALI to L. set RST to L. Turn VCC power off.

DATA COLLECTION:

The AT89C2051 Features Data polling to indicate end of write cycle.During a write cycle,an attempted read of the last byte written will result in the complement of the written data on P1.7.Data is valid on all output once the write cycle has completed and data polling may begin at any time.Once the write cycle has been after a write cycle has been initiated.

READY/BUSY :

The progress of byte programming can also be monitored by the RDY/BSY output signal.P3.1 is pulled low after p3.2 goes. High during programming to indicate BUSY. nwhen the program is done then p3.1 is pulled high again indicate READY.

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PROGRAM VERIFY

If lock bits LB1 and LB2 have not been programmed code data can be read back via the data lines for verification.

1Need to reset the internal address to bring RST from L to H

2.Apply the control signals for read code data and read the output data at the port p1 pins.

3 In internal address counter pulse pin XTAL1 should be advanced.

4.From the port p1 pins should read the next code data

Untill the entire array is read need to repeat the steps 3 and 4.

The lock bits cannot be verified directly. By observing the features are enabled Verification n of the lock bits is achieved observing that their features are enabled.

Chip erase:

In the entire PEROMT there are two lock bits are erased electrically in the entire PEROM using the proper combination of control signals and by holding p3.2 low for 10ms.The code array is written with all 1 is in chip erase operation and it must be evacuated.

Reading the signature bytes:

It can read by same procedure in the signature bytes procedure as a normal verification of locations 000H and, 002H except that p3.5 and p3.7 must be pulled to a logic low. The values returned as follows.

(000H) = 1EH indicates manufactured by Atmel

(001H) = 21H indicates 89C2051

Programming interface

Every code byte in the flash array can be written and the entire array it can be erased by combining of control signals .The operation cycle is self timed and once initiated ,will automatically time itself to completion.

Flash programming mode;

The internal PEROM address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at XATAL1 PIN.

Chip erase requires a 1oms PROG pulse.

During programmable P3.1 is pulled low to indicate RDY/BSY.

Figure 4. Verifying the Flash Memory

Additional information od dallas 1630:

Command Dallas 1630

UC

Read Temperature Reads last converted temperature

value from temperature register. Aah <read data>

Read Counter Reads value of count remaining

from counter. A0h <read data>

Read Slope Reads value of the slope

accumulator.

A9h <read data>

Start Convert T Initiates temperature conversion. EEh Idle 1

Stop Convert T Halts temperature conversion. 22h Idle 1

Write TH Writes high temperature limit value into TH register. 01h <write data> 2

Write TL Writes low temperature limit value into TL register. 02h <write data> 2

Read TH Reads stored value of high

temperature limit from TH register. A1h <read data> 2

Read TL Reads stored value of low

temperature limit from TL register. A2h <read data> 2

Write Config Writes configuration data to

configuration register. 0Ch <write data> 2

Read Config Reads configuration data ACh <read data> 2

TEMPERATURE CONVERSION COMMANDS

A stop convert T command wil halt continuous conversion in continuouys conversion mode.T command must be issused to restart the conver T and in one start conver T command must be issued for every temperature reading desired.E2 typically requires 10ms room temperature.After issuing write command no further writes should be requested for atleast 10ms.

DC ELECTRICAL CHARACTERISTICS (-55¿½C to +125¿½C; VDD=2.7V to 5.5V)

PARAMETER SYMBOL CONDITION MIN MAX UNITS NOTES

Thermometer Error TERR

0¿½C to +70¿½C

3.0V = VDD = 5.5V ¿½0.5

Degrees C 9,10

0¿½C to +70¿½C

2.7V = VDD = 3.0V ¿½1.25

-55_C to +125_C See

typical

curve

Thermometer Resolution 12 Bits

Logic 0 Output VOL 0.4 V 3

Logic 1 Output VOH 2.4 V 2

Input Resistance RI RST to GND

DQ, CLK to VDD 1

1 M_

M_

Active Supply Current ICC 0¿½C to +70¿½C 1 mA 4,5

Standby Supply Current ISTBY 0¿½C to +70¿½C 1 ¿½A

4,5

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