Synopsys For Physical Design Of Asic Computer Science Essay

IC Compiler is the software package from Synopsys for Physical Design of ASIC. It provides necessary tools to complete the back end design of the very deep submicron designs. The inputs to the IC Compiler are: a gate-level netlist which can be from DC Compiler or third-party tools, a detailed floorplan which can be from previous Design Planning through IC Compiler or other third-party tools, timing constraints and other constraints, physical and timing libraries provided by manufacturer, and foundry-process data. IC Compiler generates a GDSII-format file as output ready for tape out of the chip. In addition, it is possible to export a Design Exchange Format (DEF) file of placed netlist data ready for a third-party router. IC Compiler uses a binary Synopsys Milkyway database, which can be used by other Synopsys tools based on Milkyway. [16]

4.2 User Interfaces

IC Compiler can be used either with Shell interface (icc_shell) or with Graphical user interface (GUI). Shell interface is the command-line interface, which is used for batch mode, scripts, typing commands, and push-button type of operations. Graphical user interface (GUI) is an advanced graphical analysis and physical editing tool. Certain tasks, such as very accurately displaying the design and providing visual analysis tools, can only performed from the GUI. Also tool command language (Tcl), which is used in many applications in the EDA industry, is available to IC Compiler. Using Tcl, you can write reusable procedures and scripts.

The IC Compiler design flow is an easy-to-use, single-pass flow that provides convergent timing closure. Figure 4.1 shows the basic IC Compiler design flow, which is centered around three core commands that perform placement and optimization (place_opt), clock tree synthesis and optimization (clock_opt), and routing and postroute optimization (route_opt). [16]

icc1

Figure 4.1 – IC Compiler Design Flow [21]

For most designs, if the place_opt, clock_opt, and route_opt steps are followed, IC Compiler will provide optimal results. You can use IC Compiler to efficiently perform chip-level design planning, placement, clock tree synthesis and routing on designs with moderate timing and congestion challenges.

To further improve the quality of results for your design you can use additional commands and switches for placement, clock tree synthesis, and routing steps that IC Compiler provides.

IC Compiler design flow involves execution of following steps:

1. Set up and prepare the libraries and the design data.

2. Perform design planning and power planning.

-Design planning is to perform necessary steps to create a floorplan, determine the size of the design, create the boundary and core area, create site rows for the placement of standard cells, set up the I/O pads.

-Power planning, is to perform necessary steps to create a power plan to meet the power budget and the target leakage current.

3. Perform placement and optimization.

IC Compiler placement and optimization uses enhanced placement and synthesis technologies to generate a legalized placement for leaf cells and an optimized design, which addresses and resolves timing closure issues for the provided design. You can supplement this functionality by optimizing for power, recovering area for placement, minimizing congestion, and minimizing timing and design rule violations.

To perform placement and optimization, use the place_opt core command (or from GUI choose “Placement” menu and then “Core Placement and Optimization” sub-menu).

4. Perform clock tree synthesis and optimization.

To perform the clock tree synthesis and optimization phase, use the command clock_opt (or

choose Clock > Core Clock Tree Synthesis and Optimization in the GUI).

IC Compiler clock tree synthesis and embedded optimization solve complicated clock tree synthesis problems, such as blockage avoidance and the correlation between preroute and postroute data. Clock tree optimization improves both clock skew and clock insertion delay by performing buffer sizing, buffer relocation, gate sizing, gate relocation, level adjustment, reconfiguration, delay insertion, dummy load insertion, and balancing of interclock delays.

5. Perform routing and postroute optimization.

To perform routing and postroute optimization, use the route_opt core command (or choose Route > Core Routing and Optimization in the GUI).

As part of routing and postroute optimization, IC Compiler performs global routing, track assignment, detail routing, search and repair, topological optimization, and engineering change order (ECO) routing. For most designs, the default routing and postroute optimization setup produces optimal results. If necessary, you can supplement this functionality by optimizing routing patterns and reducing crosstalk or by customizing the

routing and postroute optimization functions for special needs.

6. Perform chip finishing and design for manufacturing tasks.

IC Compiler provides chip finishing and design for manufacturing and yield capabilities that you can apply throughout the various stages of the design flow to address process design issues encountered during chip manufacturing.

7. Save the design.

Save your design in the Milkyway format. This format is the internal database format used by IC Compiler to store all the logical and physical information about a design. [16]

4.3 How to Invoke the IC Compiler

1. Log in to the UNIX environment with the user id and password .

2. Start IC Compiler from the UNIX promt:

UNIX$ icc_shell

The xterm unix prompt turns into the IC Compiler shell command prompt.

3. Start the GUI.

icc_shell> start_gui

This window can display schematics and logical browsers, among other things, once a design is loaded.

4.4 Preparing the Design

IC Compiler uses a Milkyway design library to store design and its associated library information. This section describes how to set up the libraries, create a Milkyway design library, read your design, and save the design in Milkyway format.

These steps are explained in the following sections:

• Setting Up the Libraries

• Setting Up the Power and Ground Nets

• Reading the Design

• Annotating the Physical Data

• Preparing for Timing Analysis and RC Calculation

• Saving the Design

4.4.1 Setting Up the Libraries

IC Compiler requires both logic libraries and physical libraries. The following sections describe how to set up and validate these libraries.

• Setting Up the Logic Libraries:

IC Compiler uses logic libraries to provide timing and functionality information for all standard cells. In addition, logic libraries can provide timing information for hard macros, such as RAMs.

IC Compiler uses variables to define the logic library settings. In each session, you must define the values for the following variables (either interactively, in the .synopsys_dc.setup file, or by restoring the values saved in the Milkyway design library) so that IC Compiler can access the libraries:

• search_path

Lists the paths where IC Compiler can locate the logic libraries.

• target_library

Lists the logic libraries that IC Compiler can use to perform physical optimization.

• link_library

Lists the logic libraries that IC Compiler can search to resolve references.

• Setting Up the Physical Libraries:

IC Compiler uses Milkyway reference libraries and technology (.tf) files to provide physical library information. The Milkyway reference libraries contain physical information about the standard cells and macro cells in your technology library. In addition, these reference libraries define the placement unit tile. The technology files provide information such as the names and characteristics (physical and electrical) for each metal layer, which are technology-specific.

The physical library information is stored in the Milkyway design library. For each cell, the Milkyway design library contains several views of the cell, which are used for different physical design tasks.

If you have not already created a Milkyway library for your design (by using another tool that uses Milkyway), you need to create one by using the IC Compiler tool. If you already have a Milkyway design library, you must open it before working on your design.

This section describes how to perform the following tasks:

• Create a Milkyway design library

To create a Milkyway design library, use the create_mw_lib command (or choose File > Create Library in the GUI).

• Open a Milkyway design library

To open an existing Milkyway design library, use the open_mw_lib command (or choose File > Open Library in the GUI).

• Report on a Milkyway design library

To report on the reference libraries attached to the design library, use the -mw_reference_library option.

icc_shell>report_mw_lib-mw_reference_library design_library_name

To report on the units used in the design library, use the report_units command.

icc_shell> report_units

• Change the physical library information

To change the technology file, use the set_mw_technology_file command (or choose

File > Set Technology File in the GUI) to specify the new technology file name and the name of the design library.

• Save the physical library information

To save the technology or reference control information in a file for later use, use the

write_mw_lib_files command (or choose File > Export > Write Library File in the GUI). In a single invocation of the command, you can output only one type of file. To output both a technology file and a reference control file, you must run the command twice.

• Verifying Library Consistency:

Consistency between the logic library and the physical library is critical to achieving good results. Before you process your design, ensure that your libraries are consistent by running the check_library command. [16]

icc_shell> check_library

4.4.2 Setting Up the Power and Ground Nets

IC Compiler uses variables to define names for the power and ground nets. In each session, you must define the values for the following variables (either interactively or in the .synopsys_dc.setup file) so that IC Compiler can identify the power and ground nets:

• mw_logic0_net

By default, IC Compiler VSS as the ground net name. If you are using a different name,

you must specify the name by setting the mw_logic0_net variable.

• mw_logic1_net

By default, IC Compiler uses VDD as the power net name. If you are using a different name, you must specify the name by setting the mw_logic1_net variable.

4.4.3 Reading the Design

IC Compiler can read designs in either Milkyway or ASCII (Verilog, DEF, and SDC files) format.

• Reading a Design in Milkyway Format

• Reading a Design in ASCII Format

4.4.4 Annotating the Physical Data

IC Compiler provides several methods of annotating physical data on the design:

• Reading the physical data from a DEF file

To read a DEF file, use the read_def command (or choose File > Import > Read DEF in

the GUI).

icc_shell> read_def -allow_physical design_name.def

• Reading the physical data from a floorplan file

A floorplan file is a file that you previously created by using the write_floorplan

command (or by choosing Floorplan > Write Floorplan in the GUI).

icc_shell> read_floorplan floorplan_file_name

• Copying the physical data from another design

To copy physical data from the layout (CEL) view of one design in the current Milkyway design library to another, use the copy_floorplan command (or choose Floorplan > Copy Floorplan in the GUI). [16]

icc_shell> copy_floorplan -from design1

4.4.5 Preparing for Timing Analysis and RC Calculation

IC Compiler provides RC calculation technology and timing analysis capabilities for both

preroute and postroute data. Before you perform RC calculation and timing analysis, you

must complete the following tasks:

• Set up the TLUPlus files

You specify these files by using the set_tlu_plus_files command (or by choosing File

> Set TLU+ in the GUI).

icc_shell> set_tlu_plus_files

-tech2itf_map ./path/map_file_name.map

-max_tluplus ./path/worst_settings.tlup

-min_tluplus ./path/best_settings.tlup

• (Optional) Back-annotate delay or parasitic data

To back-annotate the design with delay information provided in a Standard Delay Format (SDF) file, use the read_sdf command (or choose File > Import > Read SDF in the GUI).

To remove annotated data from design, use the remove_annotations command.

• Set the timing constraints

At a minimum, the timing constraints must contain a clock definition for each clock signal, as well as input and output arrival times for each I/O port. This requirement ensures that all signal paths are constrained for timing.

To read a timing constraints file, use the read_sdc command (or choose File > Import >

Read SDC in the GUI).

icc_shell> read_sdc -version 1.7 design_name.sdc

• Specify the analysis mode

Semiconductor device parameters can vary with conditions such as fabrication process,

operating temperature, and power supply voltage. The set_operating_conditions command specifies the operating conditions for analysis.

• (Optional) Set the derating factors

If your timing library does not include minimum and maximum timing data, you can perform simultaneous minimum and maximum timing analysis by specifying derating factors for your timing library. Use the set_timing_derate command to specify the derating factors.

• Select the delay calculation algorithm

By default, IC Compiler uses Elmore delay calculation for both preroute and postroute delay calculations. For postroute delay calculations, you can choose to use Arnoldi delay calculation either for clock nets only or for all nets. Elmore delay calculation is faster, but its results do not always correlate with the PrimeTime and PrimeTime SI results. The Arnoldi calculation is best used for designs with smaller geometries and high resistive nets, but it requires more runtime and memory. [16]

4.4.6 Saving the Design

To save the design in Milkyway format, use the save_mw_cel command (or choose File > Save Design in the GUI). [16]

CHAPTER 5: Design Planning

5.1 Introduction

Design planning in IC Compiler provides basic floorplanning and prototyping capabilities such as dirty-netlist handling, automatic die size exploration, performing various operations with black box modules and cells, fast placement of macros and standard cells, packing macros into arrays, creating and shaping plan groups, in-place optimization, prototype global routing analysis, hierarchical clock planning, performing pin assignment on soft macros and plan groups, performing timing budgeting, converting the hierarchy, and refining the pin assignment.

Power network synthesis and power network analysis functions, applied during the feasibility phase of design planning, provide automatic synthesis of local power structures within voltage areas. Power network analysis validates the power synthesis results by performing voltage-drop and electromigration analysis. [16]

Figure 5.1 – IC Compiler Design Planning [21]

5.2 Tasks to be performed during Design Planning

• Initializing the Floorplan

• Automating Die Size Exploration

• Handling Black Boxes

• Performing an Initial Virtual Flat Placement

• Creating and Shaping Plan Groups

• Performing Power Planning

• Performing Prototype Global Routing

• Performing Hierarchical Clock Planning

• Performing In-Place Optimization

• Performing Routing-Based Pin Assignment

• Performing RC Extraction

• Performing Timing Analysis

• Performing Timing Budgeting

• Committing the Physical Hierarchy

• Refining the Pin Assignment

5.3 Initializing the Floorplan

The steps in initializing the floorplan are described below.

• Reading the I/O Constraints:

To load the top-level I/O pad and pin constraints, use the read_io_constraints command.

• Defining the Core and Placing the I/O Pads:

To define the core and place the I/O pads and pins, use the initialize_floorplan command.

• Creating Rectilinear-Shaped Blocks:

Use the initialize_rectilinear_block command to create a floorplan for rectilinear blocks from a fixed set of L, T, U, or cross-shaped templates. These templates are used to determine the cell boundary and shape of the core. To do this, use initialize_rectilinear_block -shape L|T|U|X.

• Writing I/O Constraint Information:

To write top-level I/O pad or pin constraints, use the write_io_constraints command.

Read the Synopsys Design Constraints (SDC) file (read_sdc command) to ensure that all signal paths are constrained for timing.

• Adding Cell Rows:

To add cell rows, use the add_row command.

• Removing Cell Rows:

To remove cell rows, use the cut_row command.

• Saving the Floorplan Information:

To save the floorplan information, use the write_floorplan command.

•Writing Floorplan Physical Constraints for Design Compiler Topographical Technology:

IC Compiler can now write out the floorplan physical constraints for Design Compiler

Topographical Technology (DC-T) in Tcl format. The reason for using floorplan physical constraints in the Design Compiler topographical technology mode is to accurately represent the placement area and to improve timing correlation with the post-place-and-route design. The command syntax is:

write_physical_constraints -output output_file_name -port_side [16]

Figure 5.2 – Floor Plan After Initialization [21]

5.4 Automating Die Size Exploration

This section describes how to use MinChip technology in IC Compiler to automate the processes exploring and identifying the valid die areas to determine smallest routable, die

size for your design while maintaining the relative placement of hard macros, I/O cells, and a power structure that meets voltage drop requirements. The technology is integrated into the Design Planning tool through the estimate_fp_area command. The input is a physically flat Milkyway CEL view.

5.5 Handling Black Boxes

Black boxes can be represented in the physical design as either soft or hard macros. A black box macro has a fixed height and width. A black box soft macro sized by area and utilization can be shaped to best fit the floorplan.

To handle the black boxes run the following set of commands.

set_fp_base_gate

estimate_fp_black_boxes

flatten_fp_black_boxes

create_fp_placement

place_fp_pins

create_qtm_model qtm_bb

set_qtm_technology -lib library_name

create_qtm_port -type clock $port

report_qtm_model

write_qtm_model -format qtm_bb

report_timing qtm_bb

5.6 Performing an Initial Virtual Flat Placement

The initial virtual flat placement is very fast and is optimized for wire length, congestion, and timing.

The way to perform an initial virtual flat placement is described below.

• Evaluating Initial Hard Macro Placement:

No straightforward criteria exist for evaluating the initial hard macro placement. Measuring the quality of results (QoR) of the hard macro placement can be very subjective and often depends on practical design experience.

• Specifying Hard Macro Placement Constraints:

Different methods can be use to control the preplacement of hard macros and improve the QoR of the hard macro placement.

Creating a User-Defined Array of Hard Macros

Setting Floorplan Placement Constraints On Macro Cells

Placing a Macro Cell Relative to an Anchor Object

Using a Virtual Flat Placement Strategy

Enhancing the Behavior of Virtual Flat Placement With the macros_on_edge Switch

Creating Macro Blockages for Hard Macros

Padding the Hard Macros

• Padding the Hard Macros:

To avoid placing standard cells too close to macros, which can cause congestion or DRC violations, one can set a user-defined padding distance or keepout margin around the macros. One can set this padding distance on a selected macro’s cell instance master.During virtual flat placement no other cells will be placed within the specified distance from the macro’s edges. [16]

To set a padding distance (keepout margin) on a selected macro’s cell instance master, use the set_keepout_margin command.

• Placing Hard Macros and Standard Cells:

To place the hard macros and standard cells simultaneously, use the create_fp_placement command.

• Performing Floorplan Editing:

IC Compiler performs the following floorplan editing operations.

Creating objects

Deleting objects

Undoing and redoing edit changes

Moving objects

Changing the way objects snap to a grid

Aligning movable objects

5.7 Creating and Shaping Plan Groups

This section describes how to create plan groups for logic modules that need to be physically implemented. Plan groups restrict the placement of cells to a specific region of the core area. This section also describes how to automatically place and shape objects in a design core, add padding around plan group boundaries, and prevent signal leakage and maintain signal integrity by adding modular block shielding to plan groups and soft macros.

The following steps are covered for Creating and Shaping Plan Groups.

• Creating Plan Groups:

To create a plan group, create_plan_groups command.

To remove (delete) plan groups from the current design, use the remove_plan_groups command.

• Automatically Placing and Shaping Objects In a Design Core:

Plan groups are automatically shaped, sized, and placed inside the core area based on the distribution of cells resulting from the initial virtual flat placement. Blocks (plan groups, voltage areas, and soft macros) marked fix remain fixed; the other blocks, whether or not they are inside the core, are subject to being moved or reshaped.

To automatically place and shape objects in the design core, shape_fp_blocks command.

• Adding Padding to Plan Groups:

To prevent congestion or DRC violations, one can add padding around plan group

boundaries. Plan group padding sets placement blockages on the internal and external

edges of the plan group boundary. Internal padding is equivalent to boundary spacing in the core area. External padding is equivalent to macro padding.

To add padding to plan groups, create_fp_plan_group_padding command.

To remove both external and internal padding for the plan groups, use the remove_fp_plan_group_padding command.

• Adding Block Shielding to Plan Groups or Soft Macros:

When two signals are routed parallel to each other, signal leakage can occur between the signals, leading to an unreliable design. One can protect signal integrity by adding modular block shielding to plan groups and soft macros. The shielding consists of metal rectangles that are created around the outside of the soft macro boundary in the top level of the design, and around the inside boundary of the soft macro.

To add block shielding for plan groups or soft macros, use the create_fp_block_shielding command.

To remove the signal shielding created by modular block shielding, use the remove_fp_block_shielding command. [16]

5.8 Performing Power Planning

After completed the design planning process and have a complete floorplan, one can perform power planning, as explained below.

• Creating Logical Power and Ground Connections:

To define power and ground connections, use the connect_pg_nets command.

• Adding Power and Ground Rings:

It is necessary to add power and ground rings after doing floorplanning.

To add power and ground rings, use the create_rectangular_rings command.

• Adding Power and Ground Straps:

To add power and ground straps, use the create_power_straps command.

• Prerouting Standard Cells:

To preroute standard cells, use the preroute_standard_cells command.

• Performing Low-Power Planning for Multithreshold-CMOS Designs:

One can perform floorplanning for low-power designs by employing power gating. Power gating has the potential to reduce overall power consumption substantially because it reduces leakage power as well as switching power.

• Performing Power Network Synthesis:

As the design process moves toward creating 65-nm transistors, issues related to power and signal integrity, such as power grid generation, voltage (IR) drop, and electromigration, have become more significant and complex. In addition, this complex technology lengthens the turnaround time needed to identify and fix power and signal integrity problems.

By performing power network synthesis one can preview an early power plan that reduces the chances of encountering electromigration and voltage drop problems later in the detailed power routing.

To perform the PNS, one can run the set of following commands. [16]

synthesize_fp_rail

set_fp_rail_constraints

set_fp_rail_constraints -set_ring

set_fp_block_ring_constraints

set_fp_power_pad_constraints

set_fp_rail_region_constraints

set_fp_rail_voltage_area_constraints

set_fp_rail_strategy

• Committing the Power Plan:

Once the IR drop map meets the IR drop constraints, one can run the commit_fp_rail

command to transform the IR drop map into a power plan.

• Handling TLUPlus Models in Power Network Synthesis:

Power network synthesis supports TLUPlus models.

set_fp_rail_strategy -use_tluplus true

• Checking Power Network Synthesis Integrity:

Initially, when power network synthesis first proposes a power mesh structure, it assumes that the power pins of the mesh are connected to the hard macros and standard cells in the design. It then displays a voltage drop map that one can view to determine if it meets the voltage (IR) drop constraints. After the power mesh is committed, one might discover “problem” areas in design as a result of automatic or manual cell placement. These areas are referred to as chimney areas and pin connect areas.

To Check the PNS Integrity one can run the following set of commands.

set_fp_rail_strategy -pns_commit_check_file

set_fp_rail_strategy -pns_check_chimney_file

set_fp_rail_strategy -pns_check_chimney_file pns_chimney_report

set_fp_rail_strategy -pns_check_hor_chimney_layers

set_fp_rail_strategy -pns_check_chimney_min_dist

set_fp_rail_strategy -pns_check_pad_connection file_name

set_fp_rail_strategy -pns_report_pad_connection_limit

set_fp_rail_strategy -pns_report_min_pin_width

set_fp_rail_strategy -pns_check_hard_macro_connection file_name

set_fp_rail_strategy -pns_check_hard_macro_connection_limit

set_fp_rail_strategy -pns_report_min_pin_width

• Analyzing the Power Network:

One perform power network analysis to predict IR drop at different floorplan stages on

both complete and incomplete power nets in the design.

To perform power network analysis, use the analyze_fp_rail command.

To add virtual pads, use the create_fp_virtual_pad command.

To ignore the hard macro blockages, use the set_fp_power_plan_constraints command.

• Viewing the Analysis Results:

When power and rail analysis are complete, one can check for the voltage drop and electromigration violations in the design by using the voltage drop map and the electromigration map. One can save the results of voltage drop and electromigration current density values to the database by saving the CEL view that has just been analyzed.

• Reporting Settings for Power Network Synthesis and Power Network Analysis Strategies:

To get a report of the current values of the strategies used by power network synthesis

and power network analysis by using the report_fp_rail_strategy command. [16]

5.9 Performing Prototype Global Routing

One can perform prototype global routing to get an estimate of the routability and congestion of the design. Global routing is done to detect possible congestion “hot spots” that might exist in the floorplan due to the placement of the hard macros or inadequate channel spacing.

To perform global routing, use the route_fp_proto command.

5.10 Performing Hierarchical Clock Planning

This section describes how to reduce timing closure iterations by performing hierarchical clock planning on a top-level design during the early stages of the virtual flat flow, after plan groups are created and before the hierarchy is committed. One can perform clock planning on a specified clock net or on all clock nets in the design.

• Setting Clock Planning Options:

To set clock planning options, use the set_fp_clock_plan_options command.

• Performing Clock Planning Operations:

To perform clock planning operations, use the compile_fp_clock_plan command.

• Generating Clock Tree Reports:

To generate clock tree reports, use the report_clock_tree command.

• Using Multivoltage Designs in Clock Planning:

Clock planning supports multivoltage designs. Designs in multivoltage domains operate at various voltages. Multivoltage domains are connected through level-shifter cells. A level-shifter cell is a special cell that can carry signals across different voltage areas.

• Performing Plan Group-Aware Clock Tree Synthesis in Clock Planning:

With this feature, clock tree synthesis can generate a clock tree that honors the plan groups while inserting buffers in the tree and prevent new clock buffers from being placed on top of a plan group unless they drive the entire subtree inside that particular plan group. This results in a minimum of clock feedthroughs, which makes the design easier to manage during partitioning and budgeting. [16]

5.11 Performing In-Place Optimization

In-place optimization is an iterative process that is based on virtual routing. Three types of optimizations are performed: timing improvement, area recovery, and fixing DRC violations. These optimizations preserve the netlist’s logical hierarchy as well as the physical locations of the cells.

To perform in-place optimization, use the optimize_fp_timing command.

5.12 Performing Routing-Based Pin Assignment

IC Compiler provides two ways to perform pin assignment: on soft macros (traditional pin assignment) or on plan groups (pin cutting flow).

To assign pin constraints, use the set_fp_pin_constraints command.

To assign soft macros pins, use the place_fp_pins command.

To perform Block Level Pin Assignmentuse, use the place_fp_pins -block_level command.

To align soft macro pins, use the align_fp_pins command.

To remove soft macro pin overlaps, use the remove_fp_pin_overlaps command.

5.13 Performing RC Extraction

Perform postroute RC estimation by using the extract_rc command.

5.14 Performing Timing Analysis

Use the report_timing command to generate timing reports for the design. Depending on the options selected, one can report valid paths for the entire design or for specific paths. The timing report helps evaluate why some parts of a design might not be optimized.

5.15 Performing Timing Budgeting

During the design planning stage, timing budgeting is an important step in achieving timing closure in a physically hierarchical design. The timing budgeting algorithm determines the corresponding timing boundary constraints for each top-level soft macro or plan group (block) in a design. If the timing boundary constraints for each block are met when they are implemented, the top-level timing constraints are satisfied.

Timing budgeting distributes positive and negative slack between blocks and then generates timing constraints in the Synopsys Design Constraints (SDC) format for block-level implementation.

To generate a pre-budgeting timing analysis report file, use the check_fp_timing_environment command.

To run the timing budgeter, use the allocate_fp_budgets command.

Immediately after budgeting a design, you can use the check_fp_budget_result command to perform post-budget analysis. [16]

5.16 Committing the Physical Hierarchy

This section describes how to commit the physical hierarchy after finalizing the floorplan by converting plan groups to soft macros. Committing the hierarchy creates a new level of physical hierarchy in the virtual flat design by creating CEL views for selected plan groups. After committing the physical hierarchy, you can also “uncommit” the physical hierarchy by converting the soft macros back into plan groups.

In addition, this section also describes how to propagate top-level preroutes into soft macros, recover all pushed-down objects in child cells to the top-level, and uncommit the physical hierarchy by converting soft macros back into plan groups.

To convert plan groups to soft macros, use the commit_fp_plan_groups command.

To push down physical objects to the soft macro level, use the push_down_fp_objects command.

To push up physical objects to the soft macro level, use the push_up_fp_objects command.

To uncommit the physical hierarchy, use the uncommit_fp_soft_macros command. [16]

5.17 Refining the Pin Assignment

One can analyze and evaluate the quality of the pin assignment results by checking the

placement of soft macros pins in the design and the pin alignment.

To check the placement of soft macro pins, use the check_fp_pin_assignment command.

To check the pin alignment, use the check_fp_pin_alignment command. [16]