The Instruction Set Architectures Of Arm Information Technology Essay

The Advanced RISC Machines is the most widely used 32-bit reduced instruction set computer instruction set architecture. RISC is an improvement upon the Complex Instruction Set Computing (CISC) architecture which reduces chip complexity by simpler instructions. The simplicity of the code, low cost and small size has made ARM been used widely in the world. For example, mobile phones, music players, game consoles, calculators, digital camera etc.

Pipelining architecture

Pipelining is an efficient technique which reduces the cycle time of the processor to complete one instruction per cycle. The first generation of 32-bit ARM processors had a three-stage pipeline. The first stage is fetch which it reads an instruction from memory. The second stage is decode, the instruction is decoded and the data-path control prepare for the next cycle. The third stage is execute, it performs the result. Later ARM has more than three-stages (Cortex-A8 has thirteen stages), the use of more stages of pipeline allows each stage run a smaller volume of processing per cycle which allows the processor operate a high frequency.

Conditional execution

Conditional execution is a feature of ISA that improves performance and reduces code size. By using conditional instructions, it accurately branch reduces the number of incorrect instruction fetch and decode operations. This improves performance and reduces code size by remove branches.

Hardware support for power saving

The ARM architecture has hardware support for power saving which it is simply done by using ISA to set the processor into low-power state (sleep mode/standby mode). The simplicity of the code also reduces power.

Caching

Cache is introduced in modern ARM architecture, it is equipped either on-chip or on-chip memory.

Hardware support for floating point operations

ARM has VEP architecture (Floating Point architecture) which is a hardware support for floating point operations.

Memory models

The ARM microprocessor has 32-bit address space which the maximum memory space is 232 (4G). Memory is arranged in a linear array with 232 byte locations (32-bit addresses and 32-bit processor registers). Code instructions are stored in memory space before execution. Data and code are in the same memory space. All registers are mapped into a same 32-bit memory space just like AVR.

Registers

The ARM microprocessor has 37 general registers. ARM has two types of registers: general- purpose registers and program status registers.

General-purpose registers:

31 registers and are 32 bits wide

It is visible to user

Program status registers:

6 registers that is use to keep the program status and are 32 bits wide.

1 CPSR (current Program Status Register), status of current execution is stored.

5 SPSR (Saved Program Status Register), it is use to copy the value of CPSR register.

N, Z, C and V flags

CPSR contains four flags (Figure 1) — N, Z, C and V flags.

Figure 1

N: Negative

The result will be set on bit 31. The result will be 0 or 1 by the result of 2’s complement format. N = 1 indicates a negative number in signed operations and N = 0 indicates a zero or positive number in signed operations.

Z: Zero

The result will be set on bit 30. Z = 1 indicates result of operation is zero otherwise Z = 0.

C: Carry

The result will be set on bit 29. C flag indicates an overflow/underflow on unsigned numbers. For addition, C = 1 when it produced a carry (for unsigned overflow) and other wise C = 0. For subtraction, C=0 when it produced a borrow otherwise C = 1.

V: oVerflow

The result will be set on bit 28. V flag indicates an overflow on signed number. V = 1 indicates two signed number has a carry.

User can use C and V flag for overflow, signed comparison and unsigned comparison.

Operating modes

The ARM has seven operating modes (Figure 2). User mode is the only non-privileged mode, the remaining modes are privileged mode. Privileged mode allows access to all system resources.

Figure 2

User mode: Most tasks run on user mode. It is safe because it restricts program from accessing protected resources.

FIQ (Fast interrupt processing mode) is entered when a high speed interrupt is externally accessed.

IRQ (normal interrupt processing mode) is entered when a normal interrupt is accessed.

SVC (supervisor interrupt mode) is entered when a software interrupt is encountered.

Abort mode is entered when memory faults.

Undef (undefined instruction mode) is entered when instruction is undefined.

System mode is added on ARM Architecture Version 4, it is improve version of user mode with the full access to edit CPSR. It is used for running privileged operating system tasks.

Interrupt systems

Interrupt occurs when the program change from user mode to interrupt mode (IRQ, FIQ modes). In Figure 1, we can see I and F flags are set on bit 7 and 6, I and F flags enable normal and fast interrupt. ARM is more efficient than AVI as ARM has its own stack pointer and link register. From figure 2, we can see r13 (stack pointer) and r14 (link register) are used on FIQ mode and IRQ mode, by knowing r13 and r14 it can automatically change mode without affecting other registers in previous mode. In contrast, AVI needs to update stack pointer and return address every time interrupt occurred.

Instruction Set

Instruction structure

ARM uses 32-bit instruction encoding scheme and have three operand instruction set.

Example of three-operand format (ARM7):

ADD R1, R2, R3 ;R1 = R2 +R3

AVR uses 16-bit or 8-bit instruction and can have two operands.

To have the same result as ARM instruction set, AVR needs to perform:

ADD R2, R3 ;R2 = R2 + R3

MOV R1, R2 ;R1 = R2

Addressing mode

There are five addressing mode for ARM.

Shifter operands for data processing instructions

Load and store word or unsigned byte

Load and store halfword or load singed byte

Load and store multiple

Load and store coprocessor

Conditional execution

Conditional execution is an instruction set architecture feature that is able to predict every instruction. To cut down unnecessary branches, ARM provides instruction that compares with CPSR and branch when necessary.

For example (everything.com):

ADD R0, R4, R5 ;R0 = R4 +R5

ADDPL R0, R4, R5 ;do R0 = R4 + R5 only if negative flag is clear

By checking CPSR, ARM uses less power and more efficient.

Stack operations

A stack is an area of memory which is last-in, first-out. Both of AVR and ARM have stack pointer pointing to the stack and grows down in memory. The difference of AVR and ARM is AVR uses push/pop instruction and ARM stores multiple and loads multiple instructions to get the result of push/pop instruction in AVR.

Multiple-bit shift instructions

ARM can use multiple-bit shift instruction and AVR shift by one bit.

I/O registers

Unlike AVR, ARM does not have special instructions in and out to access I/O registers. However, ARM would write the input straight into memory.

Power saving

Like AVR, ARM also has instructions for power saving. The most recent ARM — ARMv6K introduced (WFI) Wait for interrupt, WFI indicates that the processor can enter a low-power state until a wake-up event occurs

Watchdog timer

Like AVR, ARM also has a watchdog timer. The instruction wdr use in AVR is also available in ARM. The watchdog module can be reset by using PRESETn (the global reset signal) and WDOGRESn (a block specific reset signal).

Data Types

ARM supports three data types. They are 8-bit bytes, 16-bit half words and 32-bit words. ARM does not support 64-bit signed and unsigned integers. However, we can implement 64-bit by divide the number into 2 parts (32-bit each).

Conclusion

ARM is very similar to AVR, there is no clear advantage and disadvantage between two because it is suit for use in different purposes. ARM is expensive but with a faster speed compare to AVR, it is useful in large technological devices that requires large instructions/calculations. For example, Mobile phone, game console etc. AVR uses less cost, less power and it is easier to use compare to ARM.