The Very Large Scale Integration Information Technology Essay

Low power has emerged as a principal theme in todays electronics industry. The need for low power has caused a major paradigm shift where power dissipation has become as important a consideration as performance and area. This article reviews various strategies and methodologies for designing low power circuits and systems. It describes the many issues facing designers at architectural, logic, circuit and device levels and presents some of the techniques that have been proposed to overcome these difficulties. The article concludes with the future challenges that must be met to design low power, high performance systems.

Very Large Scale Integration (VLSI) defined as many transistors on a single integrated circuit. The development of VLSI systems has historically progress hand-in-hand with technology innovations. Often, fresh achievements in lithography, or semiconductor devices, or metallization have led to the introduction of new products. Conversely, market demand for particular products or specifications has greatly influenced focused research into the technology capabilities necessary to deliver the product. Many conventional VLSI systems as a result have engendered highly specialized technologies for their support.

In contrast, a characteristic of emerging VLSI products is the integration of diverse system, each of which previously required a unique technology, into a single technology platform. The driving force behind this trend is the demand in consumer and noncommercial sectors for compact, portable, wireless electronics products – the nascent “system-on-chip era (SOC)”.

Most of the achievements in dense system integration have derived from scaling in silicon VLSI processes [i] . As manufacturing has improved, it has become more cost-effective in many applications to replace a chip set with a monolithic IC: packaging cost is decreased, interconnect path shrink, power loss in I/O drivers is reduced. Further scaling to deep submicron dimensions will continue to widen the applications of VLSI system integration but also will lead to additional complexities in reliability, interconnect and lithography [ii] . This evolution is raising questions over the optimal level of integration: package level or chip level. Each has distinct advantages and some critical deficiencies for cost, reliability, and performance.

Board-level interconnection of chip sets, although a mainstay of low-cost, high-volume manufacturing, cannot provide a suitably dense integration of high-performance, core VLSI systems. Package- and chip-level integration are more practical contenders for VLSI systems implementation because of their compact dimension and short signal interconnect. They also offer a tradeoff between dense monolithic integration and application-specific technology optimization. It is unclear at this time of the pace in the further evolution of VLSI systems, although system integration will continue to influence and be influenced by technology development [iii] .

PROBLEM STATEMENT

Low-power CMOS VLSI design is very popular among VLSI manufacturers and researchers. This low-power CMOS VLSI will produce many advantages to the system in terms of reliability, costs, product lifetime and many more. However, it is not so easy to implement is since there are many factor we need to consider such as the functionality of the CMOS VLSI, the minimum voltage to make it work, the frequency and clock of the system. So, this project will help us to find methods in analyzing many techniques to achieve low-power CMOS VLSI.

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OBJECTIVE

To learn what are the methods to achieve low-power CMOS VLSI.

To analyze what is the minimum power in various low-power VLSI techniques.

To get the best method in designing the low-power VLSI.

THEORETICAL BACKGROUND OR LITERATURE REVIEW

CMOS VLSI Technology has been progressing quickly for decades. As a result, information-oriented digital computer systems based on CMOS VLSI are changing our daily life at an unprecedented pace. Currently, CMOS VLSI is still advancing at a remarkable rate. In the future, VLSI digital chips having multi-billion transistors based on deep-submicron CMOS technology using low power supply voltages will be utilized to integrate low-power, high-speed, high capacity information-oriented digital computer systems. For deep-submicron CMOS technology using low power supply voltage, the techniques required for designing low-voltage VLSI CMOS circuits are challenging. Processing technology and devices have direct impacts on the circuit designs for low-voltage CMOS VLSI systems. Low power VLSI system-oriented applications require innovative low-voltage CMOS VLSI circuits.

Since the invention of the transistors, semiconductor technology has been progressing at a rapid pace. Various semiconductor fabrication processing technologies have been developed. As shown in Fig 1.1, digital IC technologies can be divided into two groups: active substrate and inert substrate. In the active substrate group, it is divided into two categories: silicon and III-V. In the inert substrate group, there are thin-film and thick-film technologies. Depending on the property of the thin-film, they can be categorized as silicon-on-insulator (SOI), polysilicon thin-film transistors (TFT), and amorphous TFT. In the active substrate, for the III-V group, there is GaAs MESFET, heterojunction bipolar transistors (HBT), and modulation doped FETs (MODFET). Until now, silicon technologies have been most widely used in the semiconductor industry. In the silicon group, there are bipolar and MOS technologies. The bipolar technologies can be further divided into three parts: transistor-triggered logic (TTL), integrated injection logic (I2L), and emitter coupled logic (ECL). In MOS, there are PMOS, NMOS, and CMOS technologies. Combining CMOS with bipolar, BiCMOS technologies has also been developed before. Among so many digital IC technologies, CMOS technology has become the dominant technology for VLSI. In the future, CMOS technology will still be a leading technology for VLSI for several reasons. Silicon material is easy to obtain-wafer cost is cheap. In addition, CMOS circuits are less difficult to design. Compared to other devices, the physics of CMOS devices is easier to understand-CAD of the CMOS devices is easier to implement. Along with the progress in the CMOS processing technologies, performance of CMOS circuits has been improved consistently. Among all technologies, CMOS technology offers the lowest power delay product. Under an identical speed performance, the circuits realized by CMOS technology consume the least power. Therefore, under a certain power consumption limit, using CMOS technology a chip can have the most transistor count-CMOS count technology the most functions can be integrated in a chip. This is why CMOS is the dominant technology for VLSI [iv] .

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Fig 1.1 Family of digital IC

Why is low-voltage used for CMOS VLSI? As show in Fig 1.2 [v] , based on the constant voltage (CV) scaling, when the channel length is scaled down, its lateral electric field in a device increases to a large extent. Therefore, device reliability is degraded. Due to the decrease in the gate oxide thickness, the vertical electric field also increase, which leads to reduced oxide reliability. In order to reduce vertical and lateral electric fields, reduction of power supply voltage is necessary- low voltage. Along with the down-scale of the CMOS devices, device count of a CMOS VLSI chip increases quickly. Although CMOS has the lowest DC power dissipation, its dynamic power dissipation increases quickly along with the progress in the CMOS processing technology.

Fig 1.2 Lateral electric field versus channel length in the CMOS devices

As shown in Fig 1.3, power dissipation of microprocessors and digital signal processors increases along with the progress in CMOS VLSI technology [vi] . Therefore, the increased power consumption results in a raised ambient temperature. Thus the device performance is degraded and the circuit performance is less stable. Thus good packaging is required for dissipating heat of a VLSI chip. For a general plastic package, it can handle up to around 1W of power dissipation. To handle higher power dissipation up to 10W, expensive ceramic packaging is required. For present-day high-performance microprocessors, a fan or other cooling device may be required. Based on trends as shown in figure, power dissipation capability for future CMOS VLSI circuits may still be not enough. As shown in Fig 1.4, power consumption of the future CMOS VLSI chips is still going up quickly.

Fig 1.3 Power dissipation of microprocessors and digital signal processors

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The premier technology today for digital system is CMOS, owing to its inherent low-power attributes and excellent scaling to deep submicron dimensions. Total power dissipation is expressed as

P = Pdynamic + Pstatic

= (Pswitching + Pshort-circuit + Pleakage)

=

where VDD is the operating supply; f is the clock frequency; and per node an is the switching activity, cn is the switching capacitance, iscn is the short-circuit current, and ileakn is the leakage current (subthreshold conduction and junction leakage).Dynamic power is consumed when a transistor switches between “on” and “off” while static power is leaked through the transistor junctions even when it does not perform any useful work. The power dissipated under the short-circuit condition is referred to the situation when pull-up and pull-down networks are turned on simultaneously. When the gate input is at ramp up/down, the short-circuited power dissipation exists. From this expression it is apparent that the most significant reduction in power dissipation can be accomplished by scaling the operating supply.

Due to increased demands on the system performance, the clock frequency increases. Power supply can be reduced to shrink dynamic power dissipation. Via proper circuit and system design, switching activity can be reduced to decrease power dissipation. Output load capacitance can be reduced by an advanced CMOS technology or by reducing device dimensions to reduce power dissipation.

METHODOLOGY

In this project, there are five methods that we use in order to achieve low-power VLSI system which are:

Reduce VDD

This technique can be simply applied by reducing the input voltage VDD of the CMOS VLSI system.

Reduce function

Many functions of VLSI system can be reduced by reconstruct Boolean algebra and Karnaugh maps. So, this will reduce the amount of gates in the system. This technique requires the knowledge of digital system design.

Scale process

Scaling process means we increase or decrease the size of CMOS technology that we use in CMOS VLSI system design. In order to get low-power VLSI system, we need to reduce the size of CMOS technology to help VDD reduce more.

Reduce clock load

Clock load can be count on the amount of gates that connect to a clock. If we apply on an inverter, it is not a problem since it is just connect to one NMOS and one PMOS gates. However, if we apply on a bigger system, we might need more clocks in order to reduce the clock load.

Reduce clock rate

Clock rate means the frequency of a clock. According to power dissipation formula before, the power dissipation will decrease when we decrease the clock frequency.

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