Central Processing Unit Cpu Information Technology Essay

Conduct a research on history behind the inventions of computer central processing unit. Find the stages involved of the early CPU designs and developments and compare with the latest one. How much faster is the designs and development of the latest CPU as opposed to the beginning of the CPU inventions?

A bus is a communication pathway connecting two or more components or devices. By aids of diagram, explain the bus system in term of interconnection, transmission and architecture.

Introduction of Question 1

The Central Processing Unit or normally called as CPU or as processor. It is well known as the brain of the computer which is the place whereby the data is being manipulated. It will process everything from the basic instruction to multi faceted functions. CPU is contained on a tiny chip called a microprocessor which is tinier than our smallest fingernail. The chip is built up on a piece of plastic with metal wires attached to it. Every CPU has at least two basic parts such as the control unit (CU) and also the arithmetic logic unit (ALU). ALU is responsible in performing the arithmetic and logical operations while CU extracts instructions from the memory and then decodes and also executes it all. Sometimes, it will contact ALU when it needed. The CPU is in charge in conducting all the instruction which is received from the hardware components and also software programs operates on the computer. In the computing term, it is the most important fundamentals in a computer system.

(Kendall, J. E,2002)

Answer of Question 1

In the early of the year 1969, the first microprocessor which was designed by Lee Boysel was the Four-Phase Systems AL1. This system was created with an 8-bit slice which containing eight register and also an arithmetic logic unit (ALU). It was executes by using the four-phase logic and it has been used over thousands of gates with an area of 130 by 120 mils. The chip was released in the early of 1970’s. At that time, it was produced part of a nine-chip, 24-bit CPU with also three AL1’s. Later on in the year 1990’s, it AL1 was called as a microprocessor. A revelation system was constructed whereby a single AL1 produced part of a courtroom revelation computer system together also with Random Access Memory (RAM), Read Only Memory (ROM) and so on.102716269.01.01.lg.JPG

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Four-Phase AL1

In the early of November 1971, Intel Company had introduced to the world the single chip microprocessor which was the Intel 4004. It was created by the Intel engineers, Federico Faggin, Ted Hoff, and also Stanley Mazor. At first it was created for the calculator purpose. The chip was produced in two inches wafers if we compared to the latest chips which is 12 inches wafers. The size of this microprocessor is only the size of human little finger nail yet it do delivers the same computing power as the first computer which was built in the early of year 1946 whereby it filled an entire room. The circuit line width was 10 microns or 10 000 nanometres. The data will be processed in 4 bits whereby the instruction will be 8 bit long and the chip was held by 2 300 transistor. This microprocessor speed will clock at 740 KHz and also executes maximum to 92 000 single word instruction per second. It even can access 4 KB of programmes memories and 640 bytes of Random Access Memory (RAM) and it was also produced by the Intel Company with the 3-level of deep stack. Intel_4004_Package.jpg

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Intel 4004

In the early of April 1972, Intel Company introduced another processor which was Intel 8008. It was designed by Ted Hoff, Stan Mazor, Hal Feenay and also Federico Faggin. It was an early byte oriented microprocessor designed and also manufactured by the Intel Company. It was created with 8 bit Central Processing Unit (CPU) with also an external 14 bit address bus which was capable to allocate 16KB of memory. Previously, it was well known as 1201. Later on, it was made to order by the Computer Terminal Corporation (CTC) to execute an order or instruction set for their design especially for their programmable terminal which was Datapoint 2200. This microprocessor was created in order to single chip special version of CTC’s CPU design. It was to be executes as TTL logic chips. It was produced with two different speed grades such as 500 KHz and also 850 KHz. This is because, the microprocessor took the CPU from 5 till 8 cycles to implement each order or instruction. The very efficient rate of instruction implementation are from 45 000 until 100 000 instruction per second. It was also 7 level deep stacks.

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Intel 8008

Next is about the Intel 8080 which was introduced in the early of April 1974. It was designed by Federico Faggin, Masatoshi Shima and also Stan Mazor. This 8 bit or 16 bit microprocessor was created and also implement by the Intel Company. The maximum memory space or size for Intel 8080 has been increased from 16 KB to 64 KB Random Access Memory (RAM). It also have 16 bit of stack point to the memory whereby can be replaced the 8 level internal stack of the Intel 8008 and also the 16 bit of program counter. The total of the Input/ Output ports (I/O) is high till 256. Hence, the I/O devices could be connected without taking remove or interfering with the addressing space, and also the signal pin which would allow the stack to dwell in a split bank of memory. This microprocessor was used in the first widely and famous well known personal computer which was Altair 8800. It was one of of the good and high function of Intel 8080 which had been approved better than Intel 4004 and also Intel 8008. It was the first widely accepted microprocessor by the user.

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Intel 8080

After one year, Motorola had introduced a microprocessor which was known as 6800 or MOS Technology 6502. The 8 bit microprocessor was designed by Chuck Peddle and also Bill Mensch in the early of year 1975. The maximum memory space or size for this microprocessor is maximized until 64 KB Random Access Memory (RAM). 6800 which was introduced with a very low price was designed with the very low stack size. The stack size was limited until 256 bytes. This microprocessor had around six register whereby only one of the registers could be used for arithmetic and also logic operations. 6800 microprocessor was produced with very high speed which is maximized up to 14 MHz but there is Input/output (I/O) ports or instruction was created. By the time this microprocessor was introduced, it was the least price with full featured microprocessor on the market with the full package of margin, costing less than one sixth the prices of competing designs from the largest companies such as Motorola and also Intel.

(CPU WORLD,2013)

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MOS Technology 6502

(Mary Bellis)

Next is about Pentium which was produced and also manufactured by the Intel Company. This microprocessor was introduced to the market in the early of year 1993 is a very popular control processor unit whereby it is very well known for delivering excellent performance capabilities. The maximum clock rate was produced from 60 MHz to 3.8 GHz. The bus width size is around 64 bits and the microprocessor is capable to execute instruction or order till 4 GB. The address bus size is 32 bits and the microprocessor runs at 5 volts. Pentium are usually used in the desktop with 8 KB of instruction cache and also 8 KB of data cache. images.jpg

Intel Pentium

Pentium Pro was introduced in the November 1st 1995 by the Intel Company. It consists of 5.5 million transistors and the chip cache was designed at different level such as 256Kb, 512Kb, 1Mb and also 2Mb. The cache ran at the full clock speed and it was built in directly onto the processor whereby it made extremely expensive package to the manufacturer. It was the 1st processor which was produce with the Socket8 connector and it was maximized to run application up to 32 bit. It has been proved that, this processor is the most high demand in the market and very suitable for home or desktop market.

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Intel Pentium Pro

(InetDaemon.Com)

Conclusion of Question 1

The latest processor is Intel Core by company Intel. It is a brand name used for various middle ranges until the high range consumer and also microprocessor. Day by day, the processor are build with improved skills whereby fulfil the consumer demands. Core Duo, Core Solo, Core 2 Solo, Core 2 Duo, Core 2 Quad, Core 2 Extreme,  Core i3,  Core i5, Core i7, Core i3 and Core i7 is the list of Intel Core which was build with different features. The clock speed, memory space, cache power, IPC, Front Side Bus (FSB) speed, interface (socket/slot), bit width and so many features are improved each new version of processor are created.

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Introduction of Question 2

Bus is the fastest and easiest way to connect each component in a computer system is by using a direct connection. Each component is directly connected to each other. However, a direct connection is costly because it requires many connections. To connect only five components, ten connections are required. This amount of connections increases as the amount of system component increases. To save cost, most computer systems connect its components using the concept of a road. A road does not connect a house directly to another house, however, it does provide a path and each house is connected to the path. The data bus is used to transfer information about where the data should reside the memory. The size of bus is called as the bus width which responsible in determines the number of bits that the computer can transmit at one time. The larger the number that been handled by the bus, the faster the computer transfer the data. Every bus also does have its own clock speed just like the central processing unit (CPU). Manufactures state the clock speed for u bus is hertz. The higher the bus clock speed, the faster the transmission of data. Hence, it results in programs to run faster.

Variety Bus in a Computer System

(Computer Organization & Architecture)

Answer of Question 2

Normally, busses consist of multiple communication pathways or lines whereby each line of the buses are proficient of transmitting signals representing binary 1 and also binary 0. Computer system do contains a number of different buses that provide pathways between components at various level of the computer system hierarchy. System bus is a bus which connects major computer components such as processor, memory and input/output (I/O). Usually, computers interconnection structures based on the use of one or more system bus.

graphics12.jpgBus Interconnection Scheme

(William Stallings)

Naturally, system buses consists about 50 to 100 of split lines which each of the line is given specific meaning or function. Even though there are variety types of buses design, still the lines are divided into three groups such as control lines, address lines and also data lines. Between the system modules, the data lines do supply a pathway for the data to move which is called as data bus. It may consist from 32 to 100 of different line whereby all the lines are being named as the width of the data bus. The function of the width is to identify the overall performance of the system. If the data bus is 8 bits wide and each of the instruction is 16 bits long, hence the processor must access the memory twice during each of the instruction. Moreover, the data lines is used in order to allocate the destination or the direction of the data on the data bus which the data lines are normally being used in to allocate input/output (I/O) devices. Normally, the higher order bits are used to select a particular module on the bus, and the lower order bits select the memory location within the module. The control line is responsible in controlling the routine or the usage of the data and the data lines. This is because, all the data and the data lines are being shared by the entire computer. Control signals convey command and timing information between system modules. There are some examples of control line such as memory write. Memory read, I/O write, I/O read, bus request, transfer ACK, bus grant, interrupt request, interrupt ACK, clock and reset.

(sm.luth.se)

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Traditional Bus Architecture

In traditional bus architecture, local bus which is connected to the processor to a cache memory will support one or more local devices. Traditional bus architecture is very reasonable and efficient but it will start to break down when the performance of the I/O devices getting higher. Main memory can be moved off of the local bus onto a system bus. Hence, I/O will transfer to and from the main memory across the system bus do not interfere with the processor’s activity. Moreover, the cache memory controllers connect the cache not only to this local bus, but also to the system bus whereby all are attached together with me memory modules.

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(Yourdan, E. 1991)

High Performance Architecture

In high performance architecture, again the local bus that connects the processor to a cache controller whereby, it is in turn connected to the system bus which support main memory. Moreover, the cache controller is included into a bridge or else the buffering device which connect to the high speed bus. Hence, it will produce high demand devices into closer combination with the processor and it is also independent of the processor.

There are actually few master buses. To determine which device is the master bus at any one time, an arbitration mechanism that is responsible in determining the device that should use the bus at that particular time. To use this mechanism, a device known as Arbitration is required. In most microprocessors, this arbitration is developed in a CPU chip. Whereas, it is a separated devices in the minicomputer. In some systems, the CPU is also required to compete in order to obtain the bus. The CPU has the least priority in getting the bus and is only able to obtain the bus if no other devices are using the bus. This is because the CPU can wait, whereas other devices especially I/O devices, usually needs the bus immediately, if not the data will be lost.

Buses system can be divided into two categories such as synchronous and asynchronous timing. Synchronous timing occurs when a signal has a fixed relationship with a clock edge. The bus includes a clock line upon which a clock transmits a regular sequence of altering 1s and 0s of equal duration. Most of the events dwell in a single clock cycle. Meanwhile, asynchronous timing is the occurrence of any previous event. It means, means that there is no deterministic timing relationship between two devices. However, the timing requirements are less stringent than for the synchronous timing applications. Synchronous timing is much simple to implement and test rather than asynchronous timing. This is because, all the devices on a synchronous bus are tied to fixed clock rate. Hence, the system could not take any advantage of the advance in device performance. With asynchronous timing, a mixture slow and fast devices, suing older and newer technology and even can share a bus. 3.36.jpg

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(Yourdan, E. 1991)

Timing of Asynchronous Bus Operation

Finally, buses support various data transfer types. All busses support write and read transfer which is well known as master to slave and also slave to master. If there is a case of multiplexed address or data bus, hence the bus is first been used for specifying the address and also to transfer all the data. For the read operation, there is normally a wait while the data is being fetched from the slave to be put on the bus. Sometimes, there will be a delay allowed if it is necessary to go through arbitration to gain control of the bus for the remainder of the operation. In the case of dedicated address and data bus, the address is put on the address bus and then remains there while all the data are being put on the bus.

Conclusion of Question 2

This bus system is very important in order to help the central processing unit (CPU) to execute in the successful manner. CPU need helps and support from the busses system to help them to interpret and receive the multi instruction and order by the user. The clock speed in the bus system helps the system to handle the multi instruction with very faster action. The buses are used to transfer bits from input devices to memory, from memory to the processor, from processor to memory and also from memory to any output storage.

( Booch, G. 2004)

Appendixes

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